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| DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Data Sheet High-Performance, 16-bit Digital Signal Controllers (c) 2009 Microchip Technology Inc. Preliminary DS70318D Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70318D-page ii Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 High-Performance, 16-Bit Digital Signal Controllers Operating Range: * Up to 40 MIPS Operation (at 3.0-3.6V): - Industrial temperature range (-40C to +85C) - Extended temperature range (-40C to +125C) Peripheral Features: * Timer/Counters, up to Three 16-Bit Timers: - Can pair up to make one 32-bit timer * Input Capture (up to two channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture * Output Compare (up to two channels): - Single or Dual 16-Bit Compare mode - 16-Bit Glitchless PWM mode * 4-Wire SPI: - Framing supports I/O interface to simple codecs - 1-deep FIFO Buffer. - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes * I2CTM: - Supports Full Multi-Master Slave mode - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking * UART: - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA(R) encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS High-Performance DSC CPU: * * * * * * * * * Modified Harvard Architecture C Compiler Optimized Instruction Set 16-Bit Wide Data Path 24-Bit Wide Instructions Linear Program Memory Addressing up to 4M Instruction Words Linear Data Memory Addressing up to 64 Kbytes 83 Base Instructions: Mostly 1 Word/1 Cycle Two 40-Bit Accumulators with Rounding and Saturation Options Flexible and Powerful Addressing modes: - Indirect - Modulo - Bit-Reversed Software Stack 16 x 16 Fractional/Integer Multiply Operations 32/16 and 16/16 Divide Operations Single-Cycle Multiply and Accumulate: - Accumulator write back for DSP operations - Dual data fetch Up to 16-Bit Shifts for up to 40-Bit Data * * * * * Digital I/O: * * * * * * * Peripheral Pin Select Functionality Up to 35 Programmable Digital I/O Pins Wake-up/Interrupt-on-Change for up to 30 Pins Output Pins can Drive Voltage from 3.0V to 3.6V Up to 5V Output with Open-Drain Configuration 5V Tolerant Digital Input Pins (except RB5) 16 mA Source/Sink on All PWM pins Interrupt Controller: * * * * * 5-Cycle Latency Up to 35 Available Interrupt Sources Up to Three External Interrupts Seven Programmable Priority Levels Four Processor Exceptions On-Chip Flash and SRAM: * Flash Program Memory (up to 16 Kbytes) * Data SRAM (up to 2 Kbytes) * Boot and General Security for Program Flash (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 1 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 High-Speed PWM Module Features: * Up to Four PWM Generators with Four to Eight Outputs * Individual Time Base and Duty Cycle for each of the Eight PWM Outputs * Dead Time for Rising and Falling Edges * Duty Cycle Resolution of 1.04 ns * Dead-Time Resolution of 1.04 ns * Phase Shift Resolution of 1.04 ns * Frequency Resolution of 1.04 ns * PWM modes Supported: - Standard Edge-Aligned - True Independent Output - Complementary - Center-Aligned - Push-Pull - Multi-Phase - Variable Phase - Fixed Off-Time - Current Reset - Current-Limit * Independent Fault/Current-Limit Inputs for 8 PWM Outputs * Output Override Control * Special Event Trigger * PWM Capture Feature * Prescaler for Input Clock * Dual Trigger from PWM to ADC * PWMxL, PWMxH Output Pin Swapping * PWM4H, PWM4L Pins Remappable * On-the-Fly PWM Frequency, Duty Cycle and Phase Shift Changes * Disabling of Individual PWM Generators * Leading-Edge Blanking (LEB) Functionality High-Speed 10-Bit ADC * 10-Bit Resolution * Up to 12 Input Channels Grouped into Six Conversion Pairs * Two Internal Reference Monitoring Inputs Grouped into a Pair * Successive Approximation Register (SAR) Converters for Parallel Conversions of Analog Pairs: - 4 Msps for devices with two SARs - 2 Msps for devices with one SAR * Dedicated Result Buffer for each Analog Channel * Independent Trigger Source Section for each Analog Input Conversion Pair Power Management: * On-Chip 2.5V Voltage Regulator * Switch between Clock Sources in Real Time * Idle, Sleep, and Doze modes with Fast Wake-up CMOS Flash Technology: * * * * * Low-Power, High-Speed Flash Technology Fully Static Design 3.3V (10%) Operating Voltage Industrial and Extended Temperature Low-Power Consumption System Management: * Flexible Clock Options: - External, crystal, resonator, internal RC - Phase-Locked Loop (PLL) with 120 MHz VCO - Primary Crystal Oscillator (OSC) in the range of 3 MHz to 40 MHz - Internal Low-Power RC (LPRC) oscillator at a frequency of 32 kHz - Internal Fast RC (FRC) oscillator at a frequency of 7.37 MHz * Power-on Reset (POR) * Brown-out Reset (BOR) * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * Watchdog Timer with its RC Oscillator * Fail-Safe Clock Monitor (FSCM) * Reset by Multiple Sources * In-Circuit Serial ProgrammingTM (ICSPTM) * Reference Oscillator Output High-Speed Analog Comparator * Up to Four Analog Comparators: - 20 ns response time - 10-bit DAC for each analog comparator - DACOUT pin to provide DAC output - Programmable output polarity - Selectable input source - ADC sample and convert capability * PWM Module Interface: - PWM duty cycle control - PWM period control - PWM Fault detect DS70318D-page 2 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Application Examples * * * * * * * * * AC-to-DC Converters Automotive HID Battery Chargers DC-to-DC Converters Digital Lighting Induction Cooking LED Ballast Renewable Power/Pure Sine Wave Inverters Uninterruptible Power Supply (UPS) Packaging: * 18-Pin SOIC * 28-Pin SPDIP/SOIC/QFN-S * 44-Pin TQFP/QFN Note: See the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families table for the exact peripheral features per device. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 3 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families Program Flash Memory (Kbytes) Remappable Peripherals ADC Sample and Hold (S&H) Circuit Analog-to-Digital Inputs External Interrupts(3) Analog Comparator Remappable Pins RAM (Bytes) Output Compare DAC Output Input Capture 16-bit Timer DSPIC33FJ06GS101 dsPIC33FJ06GS102 18 28 6 6 256 256 8 16 2 2 0 0 1 1 1 1 1 1 2x2(1) 2x2 0 0 3 3 0 0 1 1 1 1 SARs SPI Device PWM(2) UART 3 3 6 6 13 21 SOIC SPDIP SOIC QFN-S SPDIP SOIC QFN-S SPDIP SOIC QFN-S QFN TQFP SPDIP SOIC QFN-S QFN TQFP dsPIC33FJ06GS202 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 dsPIC33FJ16GS402 28 16 2K 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 dsPIC33FJ16GS404 dsPIC33FJ16GS502 44 28 16 16 2K 2K 30 16 3 3 2 2 2 2 1 1 1 1 3x2 4x2(1) 0 4 3 3 0 1 1 1 1 2 4 6 8 8 35 21 dsPIC33FJ16GS504 44 16 2K 30 3 2 2 1 1 4x2(1) 4 3 1 1 2 6 12 35 Note 1: 2: 3: The PWM4H:PWM4L pins are remappable. The PWM Fault pins and PWM synchronization pins are remappable. Only two out of three interrupts are remappable. DS70318D-page 4 Preliminary (c) 2009 Microchip Technology Inc. Packages I/O Pins I2CTM Pins DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams 18-Pin SOIC = Pins are up to 5V tolerant MCLR AN0/RA0 AN1/RA1 AN2/RA2 AN3/RP0(1)/CN0/RB0 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 TCK/PGED2/INT0/RP3(1)/CN3/RB3 TMS/PGEC2/RP4 (1)/CN4/RB4 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD VSS PWM1L/RA3 PWM1H/RA4 VCAP/VDDCORE VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 DSPIC33FJ06GS101 28-Pin SOIC, SPDIP = Pins are up to 5V tolerant MCLR AN0/RA0 AN1/RA1 AN2/RA2 (1)/CN0/RB0 AN3/RP0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/RP1(1)/CN1/RB1 (1)/CN2/RB2 OSC2/CLKO/RP2 TCK/PGED2/INT0/RP3(1)/CN3/RB3 TMS/PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 RP12(1)/CN12/RB12 RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 dsPIC33FJ06GS102 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR AN0/CMP1A/RA0 AN1/CMP1B/RA1 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/CMP2C/RP9(1)/CN9/RB9 AN5/CMP2D/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/RP1(1)/CN1/RB1 (1) OSC2/CLKO/RP2 /CN2/RB2 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 Note 1: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals (c) 2009 Microchip Technology Inc. Preliminary dsPIC33FJ06GS202 DS70318D-page 5 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR AN0/RA0 AN1/RA1 AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 (1) OSC2/CLKO/AN7/RP2 /CN2/RB2 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/PWM3L/RP12(1)/CN12/RB12 TMS/PWM3H/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15/CN15/RB15 dsPIC33FJ16GS402 28-Pin SPDIP, SOIC MCLR AN0/CMP1A/RA0 AN1/CMP1B/RA1 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD CN8/RB8/PGED3/RP8(1)/CN8/RB8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 = Pins are up to 5V tolerant AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/PWM3L/RP12(1)/CN12/RB12 TMS/PWM3H/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN6/RB5 PGEC3/RP15(1)/CN15/RB15 Note 1: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals DS70318D-page 6 Preliminary dsPIC33FJ16GS502 (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) AN1/RA1 AN0/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 28-Pin QFN-S(2) = Pins are up to 5V tolerant AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/RP1(1)/CN1/RB1 (1) OSC2/CLKO/RP2 /CN2/RB2 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ06GS102 18 5 17 6 16 7 15 8 9 10 11 12 13 14 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 (1)/CN15/RB15 PGEC3/RP15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/CMP2C/RP9(1)/CN9/RB9 AN5/CMP2D/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/RP1(1)/CN1/RB1 (1)/CN2/RB2 OSC2/CLKO/RP2 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ06GS202 18 5 17 6 16 7 15 8 9 10 11 12 13 14 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 AN1/CMP1B/RA1 AN0/CMP1A/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 28-Pin QFN-S(2) = Pins are up to 5V tolerant PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 Note 1: 2: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 7 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) AN1/RA1 AN0/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 = Pins are up to 5V tolerant AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 (1)/CN2/RB2 OSC2/CLKO/AN7/RP2 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ16GS402 18 5 17 6 16 7 15 8 9 10 11 12 13 14 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/PWM3L/RP12(1)/CN12/RB12 TMS/PWM3H/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 28-Pin QFN-S(2) AN1/CMP1B/RA1 AN0/CMP1A/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 = Pins are up to 5V tolerant AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ16GS502 18 5 17 6 16 7 15 8 9 10 11 12 13 14 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/PWM3L/RP12(1)/CN12/RB12 TMS/PWM3H/RP11(1)/CN11/RB11 VCAP/VDDCORE VSS PGEC1/SDA/RP7(1)/CN7/RB7 Note 1: 2: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70318D-page 8 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 VDD VSS RP24(1)/CN24/RC8 44 43 42 41 40 39 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/CN22/RC6 RP19(1)/CN19/RC3 VSS VCAP/VDDCORE TMS/PWM3H/RP11(1)/CN11/RB11 TCK/PWM3L/RP12(1)/CN12/RB12 PWM2H/RP13(1)/CN13/RB13 PWM2L/RP14(1)/CN14/RB14 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 AN8/CMP4C/RP17(1)/CN17/RC1 VSS VDD RP26(1)/CN26/RC10 RP25(1)/CN25/RC9 AN5/RP10(1)/CN10/RB10 AN4/RP9(1)/CN9/RB9 AN3/RP0(1)/CN0/RB0 AN2/RA2 dsPIC33FJ16GS404 12 13 14 15 16 17 18 19 20 21 22 RP16(1)/CN16/RC0 RP29(1)/CN29/RC13 MCLR RP27(1)/CN27/RC11 RP28(1)/CN28/RC12 AN0/RA0 PWM1H/RA4 PWM1L/RA3 AVDD AVSS AN1/RA1 Note 1: 2: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. (c) 2009 Microchip Technology Inc. Preliminary RP23(1)/CN23/RC7 RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 PGED2/INT0/RP3(1)/CN3/RB3 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 DS70318D-page 9 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 44 43 42 41 40 39 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/RN22/RC6 RP19(1)/CN19/RC3 VSS VCAP/VDDCORE TMS/PWM3H/RP11(1)/CN11/RB11 TCK/PWM3L/RP12(1)/CN12/RB12 PWM2H/RP13(1)/CN13/RB13 PWM2L/RP14(1)/CN14/RB14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RP16(1)/CN16/RC0 RP29(1)/CN29/RC13 MCLR RP27(1)/CN27/RC11 RP28(1)/CN28/RC12 AN0/CMP1A/RA0 PWM1H/RA4 PWM1L/RA3 AN1/CMP1B/RA1 AVSS AVDD 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 AN8/CMP4C/RP17(1)/CN17/RC1 VSS VDD AN10/RP26(1)/CN26/RC10 AN11/RP25(1)/CN25/RC9 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN2/CMP1C/CMP2A/RA2 dsPIC33FJ16GS504 Note 1: 2: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to connect to VSS externally. DS70318D-page 10 Preliminary PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 VDD VSS RP24(1)/CN24/RC8 RP23(1)/CN23/RC7 (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 44 43 42 41 40 39 38 37 36 35 34 PGEC2/RP4(1)/CN4/RB4 PGED2/INT0/RP3(1)/CN3/RB3 VSS RP24(1)/CN24/RC8 VDD RP23(1)/CN23/RC7 RP18(1)/CN18/RC2 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/CN22/RC6 RP19(1)/CN19/RC3 VSS VCAP/VDDCORE TMS/PWM3H/RP11(1)/CN11/RB11 TCK/PWM3L/RP12(1)/CN12/RB12 PWM2H/RP13(1)/CN13/RB13 PWM2L/RP14(1)/CN14/RB14 1 2 3 4 5 6 7 8 9 10 11 dsPIC33FJ16GS404 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 RP17(1)/CN17/RC1 VSS VDD RP26(1)/CN26/RC10 RP25(1)/CN25/RC9 AN5/RP10(1)/CN10/RB10 AN4/RP9(1)/CN9/RB9 AN3/RP0(1)/CN0/RB0 AN2/RA2 RP29(1)/CN29/RC13 AVSS Note 1: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals (c) 2009 Microchip Technology Inc. Preliminary RP28 /CN28/RC12 AN0/RA0 AN1/RA1 MCLR RP27(1)/CN27/RC11 PWM1H/RA4 PWM1L/RA3 RP16(1)/CN16/RC0 AVDD (1) 13 12 18 17 16 15 14 19 22 21 20 DS70318D-page 11 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant RP23(1)/CN23/RC7 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 37 36 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 44 43 42 41 40 39 38 VDD VSS RP24(1)/CN24/RC8 35 34 PGEC2/RP4(1)/CN4/RB4 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/CN22/RC6 RP19(1)/CN19/RC3 VSS VCAP/VDDCORE TMS/PWM3H/RP11(1)/CN11/RB11 TCK/PWM3L/RP12(1)/CN12/RB12 PWM2H/RP13(1)/CN13/RB13 PWM2L/RP14(1)/CN14/RB14 1 2 3 4 5 6 7 8 9 10 11 dsPIC33FJ16GS504 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 AN8/CMP4C/RP17(1)/CN17/RC1 VSS VDD AN10/RP26(1)/CN26/RC10 AN11/RP25(1)/CN25/RC9 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN2/CMP1C/CMP2A/RA2 RP29(1)/CN29/RC13 AVSS RP28(1)/CN28/RC12 RP16(1)/CN16/RC0 PWM1H/RA4 PWM1L/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See the "DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families" table for the list of available peripherals DS70318D-page 12 Preliminary MCLR RP27(1)/CN27/RC11 AN0/CMP1A/RA0 AN1/CMP1B/RA1 AVDD 13 12 18 17 16 15 14 19 22 21 20 (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Table of Contents DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Product Families .......................................................................................... 4 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 19 3.0 CPU............................................................................................................................................................................................ 29 4.0 Memory Organization ................................................................................................................................................................. 41 5.0 Flash Program Memory.............................................................................................................................................................. 81 6.0 Resets ....................................................................................................................................................................................... 87 7.0 Interrupt Controller ..................................................................................................................................................................... 95 8.0 Oscillator Configuration ......................................................................................................................................................... 135 9.0 Power-Saving Features............................................................................................................................................................ 147 10.0 I/O Ports .................................................................................................................................................................................. 155 11.0 Timer1 ...................................................................................................................................................................................... 183 12.0 Timer2/3 features .................................................................................................................................................................... 185 13.0 Input Capture............................................................................................................................................................................ 191 14.0 Output Compare....................................................................................................................................................................... 193 15.0 High-Speed PWM..................................................................................................................................................................... 197 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 217 17.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 223 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 231 19.0 High-Speed 10-bit Analog-to-Digital Converter (ADC) ............................................................................................................. 237 20.0 High-Speed Analog Comparator .............................................................................................................................................. 259 21.0 Special Features ...................................................................................................................................................................... 263 22.0 Instruction Set Summary .......................................................................................................................................................... 271 23.0 Development Support............................................................................................................................................................... 279 24.0 Electrical Characteristics .......................................................................................................................................................... 283 25.0 Packaging Information.............................................................................................................................................................. 317 Appendix A: Revision History............................................................................................................................................................. 329 Index ................................................................................................................................................................................................. 337 The Microchip Web Site ..................................................................................................................................................................... 341 Customer Change Notification Service .............................................................................................................................................. 341 Customer Support .............................................................................................................................................................................. 341 Reader Response .............................................................................................................................................................................. 342 Product Identification System ............................................................................................................................................................ 343 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 13 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70318D-page 14 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F Family Reference Manual" sections. This document contains device-specific information for the following dsPIC33F Digital Signal Controller (DSC) devices: * * * * * * * DSPIC33FJ06GS101 dsPIC33FJ06GS102 dsPIC33FJ06GS202 dsPIC33FJ16GS402 dsPIC33FJ16GS404 dsPIC33FJ16GS502 dsPIC33FJ16GS504 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 15 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 1-1: PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch Y RAM Address Latch 16 PORTB DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Data Latch PORTA 16 16 16 Data Latch 23 16 16 PORTC Address Latch Address Generator Units Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data Remappable Pins 16 Instruction Decode & Control Control Signals to Various Blocks OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Instruction Reg 16 DSP Engine 16 x 16 W Register Array 16 Divide Support 16-Bit ALU 16 VCAP/VDDCORE VDD, VSS MCLR Timers 1-3 UART1 ADC1 OC1 OC2 PWM 4x2 Comparators 1-4 Analog IC1,2 CNx I2C1 SPI1 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70318D-page 16 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: Pin Name AN0-AN11 CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Type I I O Buffer Type Analog ST/CMOS -- PPS Capable No No No Analog input channels External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture inputs 1/2 Compare Fault A input (for Compare Channels 1 and 2) Compare Outputs 1 through 2 External Interrupt 0 External Interrupt 1 External Interrupt 2 PORTA is a bidirectional I/O port PORTB is a bidirectional I/O port PORTC is a bidirectional I/O port Remappable I/O pins Timer1 external clock input Timer2 external clock input Timer3 external clock input UART1 clear to send UART1 ready to send UART1 receive UART1 transmit Synchronous serial clock input/output for SPI1 SPI1 data in SPI1 data out SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for I2C1 Synchronous serial data input/output for I2C1 JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin Analog = Analog input I = Input P = Power O = Output PPS = Peripheral Pin Select Description OSC1 OSC2 I I/O ST/CMOS -- No No CN0-CN29 IC1-IC2 OCFA OC1-OC2 INT0 INT1 INT2 RA0-RA4 RB0-RB15 RC0-RC13 RP0-RP29 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX SCK1 SDI1 SDO1 SS1 SCL1 SDA1 TMS TCK TDI TDO I I I O I I I I/O I/O I/O I/O I I I I O I O I/O I O I/O I/O I/O I I I O ST ST ST -- ST ST ST ST ST ST ST ST ST ST ST -- ST -- ST ST -- ST ST ST TTL TTL TTL -- No Yes Yes Yes No Yes Yes No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 17 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: Pin Name CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B CMP4C CMP4D DACOUT ACMP1-ACMP4 EXTREF REFCLKO FLT1-FLT8 SYNCI1-SYNCI2 SYNCO1 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 MCLR AVDD AVSS VDD VCAP/VDDCORE VSS PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I I I I I I I I I I I I I I I I O O I O I I O O O O O O O O O I/O I I/O I I/O I I/P P P P P P Buffer Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog -- -- Analog -- ST ST -- -- -- -- -- -- -- -- -- ST ST ST ST ST ST ST P P -- -- -- PPS Capable No No No No No No No No No No No No No No No No No Yes No Yes Yes Yes Yes No No No No No No Yes Yes No No No No No No No No No No No No Comparator 1 Channel A Comparator 1 Channel B Comparator 1 Channel C Comparator 1 Channel D Comparator 2 Channel A Comparator 2 Channel B Comparator 2 Channel C Comparator 2 Channel D Comparator 3 Channel A Comparator 3 Channel B Comparator 3 Channel C Comparator 3 Channel D Comparator 4 Channel A Comparator 4 Channel B Comparator 4 Channel C Comparator 4 Channel D DAC output voltage DAC trigger to PWM module External voltage reference input for the reference DACs REFCLKO output signal is a postscaled derivative of the system clock Fault Inputs to PWM module External synchronization signal to PWM Master Time Base PWM master time base for external device synchronization PWM1 low output PWM1 high output PWM2 low output PWM2 high output PWM3 low output PWM3 high output PWM4 low output PWM4 high output Data I/O pin for programming/debugging communication Channel 1 Clock input pin for programming/debugging communication Channel 1 Data I/O pin for programming/debugging communication Channel 2 Clock input pin for programming/debugging communication Channel 2 Data I/O pin for programming/debugging communication Channel 3 Clock input pin for programming/debugging communication Channel 3 Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules Positive supply for peripheral logic and I/O pins CPU logic filter capacitor connection Ground reference for logic and I/O pins Analog = Analog input I = Input P = Power O = Output PPS = Peripheral Pin Select Description Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic DS70318D-page 18 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family Reference Manual, which is available from the Microchip website (www.microchip.com). 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: Recommendation of 0.1 F (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Note: 2.1 Basic Connection Requirements Getting started with the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of 16-bit Digital Signal Controllers (DSC) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 "Decoupling Capacitors") * VCAP/VDDCORE (see Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)") * MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 "External Oscillator Pins") (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 19 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 F Ceramic 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: * Device Reset * Device programming and debugging. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. VDD VCAP/VDDCORE R R1 MCLR C dsPIC33F VSS VDD VDD VSS AVDD AVSS VDD VSS VDD VSS 0.1 F Ceramic 0.1 F Ceramic 10 0.1 F Ceramic 0.1 F Ceramic For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. 2.2.1 TANK CAPACITORS FIGURE 2-2: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 JP C MCLR dsPIC33F 2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) Note 1: A low-ESR (< 5 Ohms) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD, and must have a capacitor between 4.7 F and 10 F, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 24.0 "Electrical Characteristics" for additional information. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 21.2 "On-Chip Voltage Regulator" for details. R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS70318D-page 20 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 2, MPLAB(R) ICD 3, or MPLAB(R) REAL ICETM. For more information on ICD 2, ICD 3, and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" DS51331 * "Using MPLAB(R) ICD 2" (poster) DS51265 * "MPLAB(R) ICD 2 Design Advisory" DS51566 * "Using MPLAB(R) ICD 3" (poster) DS51765 * "MPLAB(R) ICD 3 Design Advisory" DS51764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS51616 * "Using MPLAB(R) REAL ICETM" (poster) DS51749 Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring Guard Trace Secondary Oscillator 14 15 16 17 18 19 20 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 21 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.7 Oscillator Value Conditions on Device Start-up If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of these registers is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality. If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV, and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor to VSS on unused pins and drive the output to logic low. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins, by setting all bits in the ADPCFG register. The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 through Figure 2-11. DS70318D-page 22 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 VAC k3 k2 FET Driver ADC Channel ADC Channel PWM Output ADC Channel DSPIC33FJ06GS101 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION VINPUT IPFC VOUTPUT k1 k3 k2 FET Driver ADC Channel ADC Channel PWM Output ADC Channel DSPIC33FJ06GS101 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 23 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I5V k7 FET Driver k1 k2 FIGURE 2-7: 12V Input MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 3.3V Output PWM PWM ADC Channel Analog Comp. ADC Channel dsPIC33FJ06GS202 k7 FET Driver FET Driver k6 PWM PWM PWM PWM ADC Channel PWM PWM FET Driver k3 k4 k5 Analog Comparator dsPIC33FJ06GS502 Analog Comparator Analog Comparator ADC Channel DS70318D-page 24 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-8: OFF-LINE UPS VDC Full-Bridge Inverter Push-Pull Converter VBAT VOUT+ + VOUTGND GND FET Driver FET Driver k2 k1 FET Driver FET Driver FET Driver FET Driver k4 k5 PWM k3 ADC PWM ADC ADC or Analog Comp. PWM PWM PWM PWM ADC ADC dsPIC33FJ16GS504 ADC k6 PWM FET Driver + Battery Charger (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 25 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k1 k2 k3 VOUTFET Driver FET Driver ADC Channel PWM ADC Channel PWM ADC Channel ADC Channel ADC Channel dsPIC33FJ06GS202 DS70318D-page 26 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUTGate 4 Gate 5 Gate 6 Gate 5 Gate 2 VIN- FET Driver k1 Gate 1 FET Driver Gate 3 FET Driver PWM Analog Ground PWM ADC Channel PWM k2 S1 ADC Channel dsPIC33FJ06GS202 S3 Gate 2 Gate 4 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 27 FIGURE 2-11: Isolation Barrier VOUT IZVT AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V) ZVT with Current Doubler Synchronous Rectifier PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM DS70318D-page 28 3.3V Multi-Phase Buck Stage 12V Input I3.3V_1 3.3V Output k4 I5V FET Driver k5 k6 k7 FET Driver FET Driver I3.3V_3 k11 FET Driver VHV_BUS FET Driver FET Driver 5V Buck Stage 5V Output I3.3V_2 ADC ADC Channel Channel PWM PWM UART RX ADC Channel Analog Comp. ADC Channel Primary Controller dsPIC33FJ16GS504 ADC Ch. ADC Ch. PWM Output ADC Ch. PWM PWM Analog Comparator FET Driver k8 Analog Comparator Analog Comparator ADC Channel k9 k10 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary Secondary Controller dsPIC33FJ16GS504 FET Driver UART TX k3 VHV_BUS IPFC PFC Stage k2 VAC k1 (c) 2009 Microchip Technology Inc. |VAC| DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.0 Note: CPU This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 2. "CPU" (DS70204), which is available from the Microchip web site (www.microchip.com). 3.1 Data Addressing Overview The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies from device to device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can serve as a data, address or address offset register. The sixteenth working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. There are two classes of instruction in the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer's model for the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 is shown in Figure 3-2. The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data space mapping feature lets any instruction access program space as if it were data space. 3.2 DSP Engine Overview The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits, right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 29 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.3 Special MCU Features The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Y Data Bus X Data Bus 16 16 Data Latch X RAM Address Latch 16 Data Latch Y RAM Address Latch 16 23 16 Address Latch 16 Address Generator Units Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data 16 Instruction Decode & Control Instruction Reg 16 Control Signals to Various Blocks DSP Engine Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS70318D-page 30 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-2: DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER'S MODEL D15 W0/WREG W1 W2 W3 W4 DSP Operand Registers W5 W6 W7 W8 DSP Address Registers W9 W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD39 DSP Accumulators PC22 0 TBLPAG 7 PSVPAG 0 Program Space Visibility Page Address 15 RCOUNT 15 DCOUNT 22 DOSTART 22 DOEND 15 CORCON OA OB SA SB OAB SAB DA SRH DC IPL2 IPL1 IPL0 RA SRL N OV 0 Core Configuration Register DO Loop End Address 0 DO Loop Start Address 0 DO Loop Counter 0 REPEAT Loop Counter Data Table Page Address ACCA ACCB PC0 0 7 Program Counter AD31 Stack Pointer Limit Register AD15 AD0 Working Registers DO Shadow Legend D0 PUSH.S Shadow Z C STATUS Register (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 31 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.4 CPU Control Registers SR: CPU STATUS REGISTER R-0 OB R/C-0 SA(1) R/C-0 SB(1) R-0 OAB R/C-0 SAB(1,4) R -0 DA R/W-0 DC bit 8 R/W-0(3) IPL<2:0>(2) bit 7 Legend: C = Clearable bit S = Settable bit `1' = Bit is set bit 15 R = Readable bit W = Writable bit `0' = Bit is cleared OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed SA: Accumulator A Saturation `Sticky' Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated SB: Accumulator B Saturation `Sticky' Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed SAB: SA || SB Combined Accumulator `Sticky' Status bit(1,4) 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred U = Unimplemented bit, read as `0' -n = Value at POR x = Bit is unknown R/W-0(3) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 REGISTER 3-1: R-0 OA bit 15 R/W-0(2) bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. DS70318D-page 32 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-1: bit 7-5 SR: CPU STATUS REGISTER (CONTINUED) IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 33 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-2: U-0 -- bit 15 R/W-0 SATA bit 7 Legend: R = Readable bit 0' = Bit is cleared bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER U-0 -- U-0 -- R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 C = Clearable bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' bit 11 bit 10-8 Unimplemented: Read as `0' US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active * * * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001 = 1 DO loop active 000 = 0 DO loops active SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as `0'. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70318D-page 34 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.5 Arithmetic Logic Unit (ALU) 3.5.2 DIVIDER The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157) for information on the SR bits affected by each instruction. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: * * * * 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.6 DSP Engine The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (for example, ED, EDAC). The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below: * * * * * * Fractional or integer DSP multiply (IF) Signed or unsigned DSP multiply (US) Conventional or convergent rounding (RND) Automatic saturation on/off for ACCA (SATA) Automatic saturation on/off for ACCB (SATB) Automatic saturation on/off for writes to data memory (SATDW) * Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. 3.5.1 MULTIPLIER Using the high-speed, 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed sign operation in several MCU multiplication modes: * * * * * * * 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 35 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 3-1: CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC DSP INSTRUCTIONS SUMMARY Instruction A=0 A = (x - y)2 A = A + (x - y)2 A = A + (x * y) A = A + x2 No change in A A=x*y A=x2 A=-x*y A=A-x*y Algebraic Operation ACC Write Back Yes No No Yes No Yes No No No Yes FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate 40 Barrel Shifter 40 S a Round t 16 u Logic r a t e 40 40 16 40 Sign-Extend Y Data Bus 32 Zero Backfill 33 32 16 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70318D-page 36 Preliminary (c) 2009 Microchip Technology Inc. X Data Bus DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.6.1 MULTIPLIER 3.6.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed 2's complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit 2's complement integer is -2N-1 to 2N-1 - 1. * For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. * For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF). When the multiplier is configured for fractional multiplication, the data is represented as a 2's complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit 2's complement fraction with this implied radix point is -1.0 to (1 - 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. The MUL instruction can be directed to use byte or word-sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. * In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented). * In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: * Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. * Overflow into guard bits, 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT 3.6.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 37 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators. The device supports three Saturation and Overflow modes: * Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as `super saturation' and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). * Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set. * Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. * W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. * [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 3.6.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). * If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. * If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined: * If it is `1', ACCxH is incremented. * If it is `0', ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.6.3.2 "Data Space Write Saturation"). For the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. 3.6.3 ACCUMULATOR `WRITE BACK' The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: DS70318D-page 38 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.6.3.2 Data Space Write Saturation 3.6.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: * For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. * For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of `0' does not modify the operand. The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 39 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 40 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 4. "Program Memory" (DS70202), which is available from the Microchip web site (www.microchip.com). 4.1 Program Address Space The program address memory space of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.6 "Interfacing Program and Data Memory Spaces". User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices are shown in Figure 4-1. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access to program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAPS FOR DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DEVICES GOTO Instruction Reset Address 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 dsPIC33FJ16GS402/404/502/504 0x000000 GOTO Instruction 0x000002 Reset Address 0x000004 Interrupt Vector Table 0x0000FE 0x000100 Reserved 0x000104 Alternate Vector Table 0x0001FE 0x000200 User Program Flash Memory (5376 instructions) 0x002BFE 0x002C00 DSPIC33FJ06GS101/102/202 Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (1792 instructions) User Memory Space User Memory Space 0x000FFE 0x001000 Unimplemented (Read `0's) 0x7FFFFE 0x800000 Unimplemented (Read `0's) 0x7FFFFE 0x800000 Reserved Reserved Configuration Memory Space Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Configuration Memory Space Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Reserved Reserved DEVID (2) Reserved 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE 0xFEFFFE DEVID (2) Reserved 0xFF0000 0xFF0002 0xFFFFFE (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 41 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (see Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during the code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. All DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 "Interrupt Vector Table". FIGURE 4-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70318D-page 42 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU has a separate, 16-bitwide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 4.6.3 "Reading Data From Program Memory Using Program Space Visibility"). DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement up to 30 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. 4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. The first 2 Kbytes of the near data space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. Note: The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC(R) MCU devices and improve data space memory usage efficiency, the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] that results in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 4.2.4 NEAR DATA SPACE The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 43 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR DSPIC33FJ06GS101/102 DEVICES WITH 256 BYTES OF RAM MSB Address MSb 2-Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x087F 0x0881 0x08FF 0x0901 0x1FFF 0x2001 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x087E 0x0880 0x08FE 0x0900 0x1FFE 0x2000 8-Kbyte Near Data Space LSB Address LSb 0x0000 16 bits 256 bytes SRAM Space 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70318D-page 44 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1-Kbyte RAM MSB Address MSb 2-Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x09FF 0x0A01 0x0BFF 0x0C01 0x1FFF 0x2001 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x09FE 0x0A00 0x0BFE 0x0C00 0x1FFE 0x2000 8-Kbyte Near Data Space LSB Address LSb 0x0000 16 bits 1-Kbyte SRAM Space 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 45 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH 2-Kbyte RAM MSB Address MSb 2-Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x0BFF 0x0C01 0x0FFF 0x1001 0x1FFF 0x2001 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x0BFE 0x0C00 0x0FFE 0x1000 0x1FFE 0x2000 8-Kbyte Near Data Space LSB Address LSb 0x0000 16 bits 2-Kbyte SRAM Space 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70318D-page 46 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.5 X AND Y DATA SPACES The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms, such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 47 TABLE 4-1: Bit 14 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register ACCAL ACCAH ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCBL ACCBH ACCB<39> ACCB<39> ACCB<39> ACCB<39> -- -- -- -- -- -- -- -- -- -- -- -- -- DCOUNT<15:0> DOSTARTL<15:1> -- -- OB -- YMODEN -- -- -- US SA SB -- -- -- OAB EDT -- -- -- -- -- SAB -- DOENDL<15:1> -- DA DL<2:0> BWM<3:0> -- DC -- IPL2 SATA -- IPL1 SATB IPL0 SATD W YWM<3:0> RA ACCSAT DOENDH N IPL3 OV PSV Z RND XWM<3:0> C IF -- -- -- DOSTARTH<5:0> 0 0 -- -- -- -- -- ACCB<39> ACCB<39> ACCB<39> -- -- -- ACCBU Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register Program Counter Low Word Register ACCA<39> ACCA<39> ACCA<39> ACCAU Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 xxxx xxxx xxxx 00xx xxxx 00xx 0000 0020 0000 CPU CORE REGISTER MAP SFR Name SFR Addr Bit 15 WREG0 0000 WREG1 0002 DS70318D-page 48 Repeat Loop Counter Register WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 WREG12 0018 WREG13 001A WREG14 001C WREG15 001E SPLIM 0020 ACCAL 0022 ACCAH 0024 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary ACCAU 0026 ACCA<39> ACCBL 0028 ACCBH 002A ACCBU 002C ACCB<39> PCL 002E PCH 0030 -- TBLPAG 0032 -- PSVPAG 0034 -- RCOUNT 0036 DCOUNT 0038 DOSTARTL 003A DOSTARTH 003C -- DOENDL 003E DOENDH 0040 -- SR 0042 OA CORCON 0044 -- MODCON 0046 XMODEN (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-1: Bit 14 XS<15:1> XE<15:1> YS<15:1> YE<15:1> XB<14:0> -- Disable Interrupts Counter Register 0 1 0 1 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU CORE REGISTER MAP (CONTINUED) All Resets xxxx xxxx xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 -- (c) 2009 Microchip Technology Inc. Bit 13 -- -- CN7PUE CN6PUE CN5PUE -- -- -- -- -- -- -- -- -- -- CN7IE CN6IE CN5IE CN4IE CN4PUE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CN3IE CN3PUE Bit 2 CN2IE CN2PUE Bit 1 CN1IE CN1PUE Bit 0 CN0IE CN0PUE -- -- Bit 13 CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 CN6IE Bit 5 CN5IE CN5PUE Bit 4 CN4IE CN4PUE Bit 3 CN3IE CN3PUE Bit 2 CN2IE CN2PUE Bit 1 CN1IE CN1PUE Bit 0 CN0IE CN0PUE Bit 13 CN13IE CN29IE CN28IE CN27IE CN26IE CN12IE CN11IE CN10IE CN9IE CN25IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CN8IE CN24IE CN8PUE Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE CN19IE CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR DSPIC33FJ06GS101 All Resets 0000 0000 File Name SFR Addr Bit 15 Bit 14 CNEN1 0060 -- CNPU1 0068 -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND dsPIC33FJ16GS502 All Resets 0000 0000 File Name SFR Addr Bit 15 Bit 14 CNEN1 0060 CN15IE CN14IE CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504 All Resets 0000 0000 0000 0000 File Name SFR Addr Bit 15 Bit 14 CNEN1 0060 CN15IE CN14IE CNEN2 0062 -- -- CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 006A -- -- DS70318D-page 49 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-5: Bit 13 OVBERR COVAERR COVBERR OVATE -- ADIF INT2IF -- -- -- -- -- ADIE INT2IE -- -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- -- -- -- -- -- ADCP1IP<2:0> -- -- -- -- -- -- ILR<3:0> -- -- -- -- -- ADCP0IP<2:0> -- -- -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --- -- SPI1IP<2:0> -- -- -- -- -- -- -- -- OC1IP<2:0> -- -- -- -- SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- INT2IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- PWM4IP<2:0> -- ADCP3IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IE CNIE U1TXIE U1RXIE SPI1IE SPI1EIE -- T2IE -- -- -- T1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIF -- -- -- -- -- -- -- -- U1EIF -- PWM4IF ADCP3IF -- MI2C1IE -- -- U1EIE -- PWM4IE ADCP3IE INT0IP<2:0> -- -- U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IF CNIF -- MI2C1IF U1TXIF U1RXIF SPI1IF SPI1EIF -- T2IF -- -- -- T1IF OC1IF -- -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP OVBTE COVTE SFTACERR DIV0ERR -- MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF -- -- -- -- -- INT0IE SI2C1IE -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4404 4000 4440 0044 4044 0004 0040 0040 0400 0040 4400 0040 0000 0000 INTERRUPT CONTROLLER REGISTER MAP FOR DSPIC33FJ06GS101 DEVICES ONLY File Name SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR DS70318D-page 50 INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 -- -- IFS3 008A -- -- IFS4 008C -- -- IFS5 008E -- PWM1IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 -- -- IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E -- PWM1IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- IPC0 00A4 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC7 00B2 -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC23 00D2 -- -- IPC24 00D4 -- -- IPC27 00DA -- IPC28 00DC -- -- INTTREG 00E0 -- -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-6: Bit 13 OVBERR COVAERR COVBERR OVATE -- ADIF INT2IF -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- -- -- -- PWM2IP<2:0> ADCP1IP<2:0> -- -- -- ILR<3:0> -- -- -- -- -- -- PWM1IP<2:0> ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --- -- SPI1IP<2:0> -- -- -- -- -- -- -- -- OC1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- INT2IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIE -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IE U1TXIE U1RXIE SPI1IE SPI1EIE -- T2IE -- -- -- T1IE CNIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IF CNIF -- U1TXIF U1RXIF SPI1IF SPI1EIF -- T2IF -- -- -- T1IF OC1IF -- MI2C1IF -- U1EIF -- -- -- -- MI2C1IE -- U1EIE -- -- -- INT0IP<2:0> -- -- U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- -- -- -- -- ADCP2IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP OVBTE COVTE SFTACERR DIV0ERR -- MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF -- -- -- -- ADCP2IF INT0IE SI2C1IE -- -- -- -- ADCP2IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4404 4000 4440 0044 4044 0004 0040 0040 0040 4400 4400 0004 0000 File Name SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 -- -- IFS3 008A -- -- IFS4 008C -- -- (c) 2009 Microchip Technology Inc. IFS5 008E PWM2IF PWM1IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- IPC0 00A4 -- IPC1 00A6 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC7 00B2 -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC23 00D2 -- IPC27 00DA -- IPC28 00DC -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70318D-page 51 TABLE 4-7: Bit 13 OVBERR -- ADIF INT2IF -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- -- -- -- PWM2IP<2:0> AC2IP<2:0> ADCP1IP<2:0> -- -- -- -- -- -- -- ILR<3:0> -- -- -- -- -- -- -- -- -- ADCP0IP<2:0> -- -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AC1IP<2:0> -- -- -- -- -- -- -- --- -- SPI1IP<2:0> -- -- -- -- -- -- -- -- SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- INT2IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- OC1IP<2:0> -- -- -- -- -- -- -- -- -- IC1IP<2:0> -- -- -- -- -- -- AC2IE -- -- -- ADCP6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IE CNIE U1TXIE U1RXIE SPI1IE SPI1EIE -- T2IE -- -- -- T1IE -- -- -- -- -- -- -- -- ADCP6IF -- -- OC1IE AC1IE -- -- -- -- -- -- -- -- -- -- AC2IF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIF -- -- -- -- -- -- -- -- U1EIF -- -- -- IC1IE MI2C1IE -- U1EIE -- -- -- INT0IP<2:0> -- -- U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- -- -- -- -- -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IF CNIF AC1IF MI2C1IF U1TXIF U1RXIF SPI1IF SPI1EIF -- T2IF -- -- -- T1IF OC1IF IC1IF -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP INT0EP INT0IF SI2C1IF -- -- -- -- ADCP2IF INT0IE SI2C1IE -- -- -- -- ADCP2IE COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR -- MATHERR ADDRERR STKERR OSCFAIL -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4000 4440 0044 4444 0004 0040 0040 0040 4400 4000 4400 0004 0004 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06G202 DEVICES ONLY File Name SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR DS70318D-page 52 INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 -- -- IFS3 008A -- -- IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- IPC0 00A4 -- IPC1 00A6 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC7 00B2 -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC23 00D2 -- IPC25 00D6 -- IPC27 00DA -- IPC28 00DC -- -- IPC29 00DE -- -- INTTREG 00E0 -- -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-8: Bit 13 OVBERR COVAERR COVBERR OVATE OVBTE -- ADIF INT2IF -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- -- -- -- PWM2IP<2:0> -- ADCP1IP<2:0> -- -- -- -- -- -- ILR<3:0> -- -- -- -- -- ADCP0IP<2:0> -- -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --- -- --- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --- -- SPI1IP<2:0> -- -- OC2IP<2:0> -- -- OC1IP<2:0> -- -- -- -- -- -- -- -- -- IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- INT2IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- -- -- ADCP3IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIE -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE -- T1IE CNIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC1IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IF CNIF -- U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF -- T1IF OC1IF IC1IF MI2C1IF -- U1EIF -- -- ADCP3IF IC1IE MI2C1IE -- U1EIE -- -- ADCP3IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- -- -- -- PWM3IP<2:0> -- ADCP2IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP COVTE SFTACERR DIV0ERR -- MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF -- -- -- PWM3IF ADCP2IF INT0IE SI2C1IE -- -- -- PWM3IE ADCP2IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4044 0004 0040 0040 0040 4400 0004 4400 0044 0000 File Name SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 -- -- IFS3 008A -- -- IFS4 008C -- -- (c) 2009 Microchip Technology Inc. IFS5 008E PWM2IF PWM1IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- IPC0 00A4 -- IPC1 00A6 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC7 00B2 -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC23 00D2 -- IPC24 00D4 -- -- IPC27 00DA -- IPC28 00DC -- -- INTTREG 00E0 -- -- DS70318D-page 53 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-9: Bit 13 OVBERR COVAERR COVBERR OVATE -- ADIF INT2IF -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- -- -- -- PWM2IP<2:0> -- AC2IP<2:0> -- ADCP1IP<2:0> -- -- -- -- -- -- -- ILR<3:0> -- -- -- -- -- -- -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AC1IP<2:0> -- -- -- --- -- --- -- SPI1IP<2:0> -- -- OC2IP<2:0> -- -- OC1IP<2:0> -- IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- INT2IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- PWM4IP<2:0> -- AC4IP<2:0> -- ADCP3IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AC4IE AC3IE AC2IE -- -- -- ADCP6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIE -- -- -- -- -- -- -- -- -- -- -- --- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IE CNIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE -- T1IE -- -- -- -- -- -- -- -- ADCP6IF -- -- OC1IE AC1IE -- -- -- -- -- -- -- -- AC4IF AC3IF AC2IF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIF -- -- -- -- -- -- -- -- U1EIF -- PWM4IF ADCP3IF IC1IE MI2C1IE -- U1EIE -- PWM4IE ADCP3IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- -- -- -- PWM3IP<2:0> -- AC3IP<2:0> -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IF CNIF AC1IF MI2C1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF -- T1IF OC1IF IC1IF -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP INT0EP INT0IF SI2C1IF -- -- -- PWM3IF ADCP2IF INT0IE SI2C1IE -- -- -- PWM3IE ADCP2IE OVBTE COVTE SFTACERR DIV0ERR -- MATHERR ADDRERR STKERR OSCFAIL -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 0040 0040 0040 4400 0044 4000 0044 4400 0044 0004 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY File Name SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR DS70318D-page 54 INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 -- -- IFS3 008A -- -- IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- IPC0 00A4 -- IPC1 00A6 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC7 00B2 -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC23 00D2 -- IPC24 00D4 -- -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- -- IPC29 00DE -- -- INTTREG 00E0 -- -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-10: Bit 13 OVBERR COVAERR COVBERR -- ADIF INT2IF -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- -- -- -- PWM2IP<2:0> -- AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- -- -- -- -- ILR<3:0> -- -- -- -- -- -- -- -- ADCP0IP<2:0> ADCP4IP<2:0> -- -- -- -- -- -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AC1IP<2:0> -- -- -- -- -- -- -- --- -- SPI1IP<2:0> -- -- OC2IP<2:0> -- -- OC1IP<2:0> -- -- -- -- -- -- -- -- -- IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- INT2IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- PWM4IP<2:0> -- AC4IP<2:0> -- ADCP3IP<2:0> -- -- -- -- -- -- -- -- -- AC4IE AC3IE AC2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP6IE -- -- -- PSEMIE -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE -- T1IE CNIE -- -- -- -- ADCP5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP6IF ADCP5IF -- -- -- AC4IF AC3IF AC2IF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP4IF OC1IE AC1IE -- -- -- -- ADCP4IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSEMIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT1IF CNIF AC1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF -- T1IF OC1IF IC1IF MI2C1IF -- U1EIF -- PWM4IF ADCP3IF IC1IE MI2C1IE -- U1EIE -- PWM4IE ADCP3IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- -- -- -- PWM3IP<2:0> -- AC3IP<2:0> -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP OVATE OVBTE COVTE SFTACERR DIV0ERR -- MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF -- -- -- PWM3IF ADCP2IF INT0IE SI2C1IE -- -- -- PWM3IE ADCP2IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 0040 0040 0040 4400 0044 4000 0440 4400 4444 0004 0000 File Name SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 -- -- IFS3 008A -- -- IFS4 008C -- -- (c) 2009 Microchip Technology Inc. IFS5 008E PWM2IF PWM1IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- IPC0 00A4 -- IPC1 00A6 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC7 00B2 -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC23 00D2 -- IPC24 00D4 -- -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- DS70318D-page 55 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-11: Bit 13 Timer1 Register Period Register 1 -- Timer2 Register Period Register 2 -- TSIDL -- -- -- -- -- -- TGATE TCKPS<1:0> -- -- TCS -- TSIDL -- -- -- -- -- -- TGATE TCKPS<1:0> -- TSYNC TCS -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF 0000 xxxx FFFF 0000 TIMER REGISTER MAP FOR DSPIC33FJ06GS101 AND dsPIC33FJ06GSX02 SFR Name SFR Addr Bit 15 Bit 14 TMR1 0100 PR1 0102 DS70318D-page 56 Bit 13 Timer1 Register Period Register 1 -- Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 -- -- TSIDL -- -- -- -- -- -- TSIDL -- -- -- -- -- -- TGATE TGATE TCKPS<1:0> TCKPS<1:0> T32 -- -- -- TCS TCS -- -- TSIDL -- -- -- -- -- -- TGATE TCKPS<1:0> -- TSYNC TCS -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Input Capture 1 Register -- ICSIDL -- -- -- -- -- ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx 0000 T1CON 0104 TON TMR2 0106 PR2 010C T2CON 0110 TON Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-12: TIMER REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04 SFR Name SFR Addr Bit 15 Bit 14 TMR1 0100 PR1 0102 T1CON 0104 TON TMR2 0106 TMR3HLD 0108 TMR3 010A DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary PR2 010C PR3 010E T2CON 0110 TON T3CON 0112 TON Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-13: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ06GS202 SFR Name SFR Addr Bit 15 Bit 14 IC1BUF 0140 IC1CON 0142 -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-14: Bit 13 Input Capture 1 Register -- Input Capture 2 Register -- ICSIDL -- -- -- -- -- ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> ICSIDL -- -- -- -- -- ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04 All Resets xxxx 0000 xxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 IC1BUF 0140 IC1CON 0142 -- IC2BUF 0144 IC2CON 0146 -- (c) 2009 Microchip Technology Inc. Bit 13 Output Compare 1 Secondary Register Output Compare 1 Register -- OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 13 Output Compare 1 Secondary Register Output Compare 1 Register -- OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Compare 2 Secondary Register Output Compare 2 Register -- OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> Bit 13 PTSIDL -- -- -- SESTAT SEIEN Bit 12 Bit 11 Bit 10 EIPU -- Bit 9 SYNCPOL -- Bit 8 SYNCOEN -- PTPER<15:0> SEVTCMP<15:3> MDC<15:0> -- -- -- Bit 7 SYNCEN -- Bit 6 -- -- Bit 5 Bit 4 SYNCSRC<1:0> -- -- -- Bit 3 Bit 2 Bit 1 SEVTPS<3:0> PCLKDIV<2:0> Bit 0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-15: OUTPUT COMPARE REGISTER MAP DSPIC33FJ06GS101 AND dsPIC33FJ06GSX02 All Resets xxxx xxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 OC1RS 0180 OC1R 0182 OC1CON 0184 -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-16: OUTPUT COMPARE REGISTER MAP dsPIC33FJ16GSX02 AND dsPIC33FJ06GSX04 All Resets xxxx xxxx 0000 xxxx xxxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary OC1RS 0180 OC1R 0182 OC1CON 0184 -- OC2RS 0186 OC2R 0188 OC2CON 018A -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-17: HIGH-SPEED PWM REGISTER MAP All Resets 0000 0000 FFF8 0000 0000 File Name Addr Offset Bit 15 Bit 14 PTCON 0400 PTEN PTCON2 0402 -- PTPER 0404 SEVTCMP 0406 MDC 040A DS70318D-page 57 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-18: Bit 13 FLTIEN POLL CLSRC<4:0> PDC1<15:0> PHASE1<15:0> -- -- SDC1<15:0> SPHASE1<15:0> TRGCMP<15:3> TRGDIV<3:0> -- STRGCMP<15:3> PWMCAP1<15:3> PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> -- -- -- DTM -- -- TRGSTRT<5:0> -- -- -- -- -- -- -- -- -- -- -- ALTDTR1<13:0> DTR1<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP CLIEN TRGIEN ITB MDCS DTC<1:0> -- -- -- CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 HIGH-SPEED PWM GENERATOR 1 REGISTER MAP File Name Addr Offset Bit 15 Bit 14 PWMCON1 POLH 0420 FLTSTAT CLSTAT TRGSTAT DS70318D-page 58 FLTMOD<1:0> Bit 13 TRGSTAT POLH CLSRC<4:0> CLPOL CLMOD PDC2<15:0> PHASE2<15:0> -- -- DTR2<13:0> ALTDTR2<13:0> SDC2<15:0> SPHASE2<15:0> TRGCMP<15:3> TRGDIV<3:0> -- -- -- STRGCMP<15:3> PWMCAP2<15:3> PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> -- DTM -- -- TRGSTRT<5:0> -- -- -- -- -- -- -- -- -- -- -- POLL PMOD<1:0> OVRENH OVRENL FLTIEN CLIEN TRGIEN ITB MDCS Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 -- DTC<1:0> OVRDAT<1:0> Bit 4 -- FLTDAT<1:0> FLTSRC<4:0> Bit 3 -- Bit 2 CAM CLDAT<1:0> FLTPOL Bit 1 XPRES SWAP Bit 0 IUE OSYNC FLTMOD<1:0> All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 IOCON1 0422 PENH PENL FCLCON1 0424 IFLTMOD PDC1 0426 PHASE1 0428 DTR1 042A -- ALTDTR1 042C -- SDC1 042E SPHASE1 0430 TRIG1 0432 TRGCON1 0434 STRIG1 0436 PWMCAP1 0438 LEBCON1 043A PHR Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary TABLE 4-19: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33FJ06GS102/202 AND dsPIC33FJ16GSX02/X04 DEVICES ONLY File Name Addr Offset Bit 15 Bit 14 PWMCON2 0440 FLTSTAT CLSTAT IOCON2 0442 PENH PENL FCLCON2 0444 IFLTMOD PDC2 0446 PHASE2 0448 DTR2 044A -- ALTDTR2 044C -- SDC2 044E SPHASE2 0450 TRIG2 0452 TRGCON2 0454 STRIG2 0456 PWMCAP2 0458 LEBCON2 045A PHR (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-20: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC3<15:0> PHASE3<15:0> -- -- SDC3<15:0> SPHASE3<15:0> TRGCMP<15:3> TRGDIV<3:0> -- STRGCMP<15:3> PWMCAP3<15:3> PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> -- -- -- DTM -- -- TRGSTRT<5:0> -- -- -- -- -- -- -- -- -- -- -- ALTDTR3<13:0> DTR3<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> -- -- -- CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED PWM GENERATOR 3 REGISTER MAP FOR dsPIC33FJ16GSX02/X04 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Offset Bit 15 Bit 14 PWMCON3 0460 FLTSTAT CLSTAT IOCON3 0462 PENH PENL FCLCON3 0464 IFLTMOD FLTMOD<1:0> PDC3 0466 PHASE3 0468 DTR3 046C -- (c) 2009 Microchip Technology Inc. Bit 13 TRGSTAT POLH CLSRC<4:0> CLPOL POLL PMOD<1:0> OVRENH FLTIEN CLIEN TRGIEN ITB MDCS OVRENL CLMOD PDC4<15:0> PHASE4<15:0> -- -- DTR4<13:0> ALTDTR4<13:0> SDC4<15:0> SPHASE4<15:0> TRGCMP<15:3> TRGDIV<3:0> -- -- -- STRGCMP<15:3> PWMCAP4<15:3> PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3> -- DTM -- -- TRGSTRT<5:0> -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 DTC<1:0> OVRDAT<1:0> Bit 5 -- Bit 4 -- FLTDAT<1:0> FLTSRC<4:0> Bit 3 -- Bit 2 CAM CLDAT<1:0> FLTPOL Bit 1 XPRES SWAP Bit 0 IUE OSYNC FLTMOD<1:0> ALTDTR3 046C -- SDC3 046E SPHASE3 0470 TRIG3 0472 TRGCON3 0474 STRIG3 0476 PWMCAP3 0478 LEBCON3 047A PHR Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-21: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR DSPIC33FJ06GS101 AND dsPIC33FJ16GS50X DEVICES ONLY All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary File Name Addr Offset Bit 15 Bit 14 PWMCON4 0480 FLTSTAT CLSTAT IOCON4 0482 PENH PENL FCLCON4 0484 IFLTMOD PDC4 0486 PHASE4 0488 DTR4 048A -- ALTDTR4 048A -- SDC4 048E SPHASE4 0490 TRIG4 0492 TRGCON4 0494 STRIG4 0496 PWMCAP4 0498 LEBCON4 049A PHR DS70318D-page 59 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-22: Bit 13 -- -- -- I2CSIDL SCLREL -- -- -- -- -- -- AMSK<9:0> -- -- -- Address Register -- -- BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN -- -- -- -- Baud Rate Generator Register SEN TBF -- -- -- -- -- Transmit Register -- -- -- -- -- Receive Register Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 1000 0000 0000 0000 I2C1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 I2C1RCV 0200 -- -- DS70318D-page 60 Bit 13 USIDL -- -- -- Baud Rate Generator Prescaler -- -- -- -- -- -- UTXBRK UTXE N UTXBF TRMT URXISEL<1:0> ADDEN IREN RTSMD -- UEN1 UEN0 WAKE LPBACK ABAUD URXINV RIDLE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BRGH PERR Bit 2 Bit 1 PDSEL<1:0> FERR OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 -- -- -- -- -- UART Transmit Register UART Receive Register Bit 13 SPISIDL -- FRMPOL -- -- -- -- DISSCK DISSDO MODE16 SMP CKE -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 -- SSEN -- Bit 6 SPIROV CKP -- Bit 5 -- MSTEN -- -- Bit 4 -- Bit 3 -- SPRE<2:0> -- -- Bit 2 -- Bit 1 SPITBF Bit 0 SPIRBF PPRE<1:0> FRMDLY -- All Resets 0000 0000 0000 0000 -- -- SPI1 Transmit and Receive Buffer Register I2C1TRN 0202 -- -- I2C1BRG 0204 -- -- I2C1CON 0206 I2CEN -- I2C1STAT 0208 ACKSTAT TRSTAT I2C1ADD 020A -- -- I2C1MSK 020C -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-23: UART1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 U1TXREG 0224 -- U1RXREG 0226 -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary U1BRG 0228 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-24: SPI1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 SPI1STAT 0240 SPIEN SPI1CON1 0242 -- SPI1CON2 0244 FRMEN SPIFSD SPI1BUF 0248 (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-25: Bit 13 ADSIDL -- -- ADBASE<15:1> SWTRG1 SWTRG3 -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 6 ADC Data Buffer 7 -- -- -- -- TRGSRC3<4:0> -- TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> -- -- -- -- -- -- -- -- -- -- -- P3RDY -- -- -- -- -- -- PCFG7 PCFG6 -- -- PCFG3 PCFG2 SLOWCLK -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> PCFG1 PCFG0 P1RDY P0RDY -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED 10-BIT ADC REGISTER MAP FOR DSPIC33FJ06GS101 DEVICES ONLY All Resets 0003 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- ADPCFG 0302 -- -- ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C IRQEN3 PEND3 (c) 2009 Microchip Technology Inc. Bit 13 ADSIDL -- -- ADBASE<15:1> SWTRG1 -- -- -- -- -- -- TRGSRC1<4:0> IRQEN0 IRQEN2 PEND0 PEND2 SWTRG0 SWTRG2 TRGSRC0<4:0> TRGSRC2<4:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- SLOWCLK -- GSWTRG -- FORM EIE ORDER Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 SEQSAMP PCFG5 -- Bit 4 ASYNCSAMP PCFG4 -- Bit 3 -- PCFG3 -- Bit 2 Bit 1 ADCS<2:0> PCFG2 P2RDY PCFG1 PCFG0 P1RDY P0RDY -- Bit 0 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADCBUF0 0320 ADCBUF1 0322 ADCBUF2 0324 ADCBUF3 0326 ADCBUF6 032C ADCBUF7 032E Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-26: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY All Resets 0003 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary ADPCFG 0302 -- -- ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C -- -- ADCBUF0 0320 ADCBUF1 0322 ADCBUF2 0324 ADCBUF3 0326 ADCBUF4 0328 ADCBUF5 032A Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70318D-page 61 TABLE 4-27: Bit 13 ADSIDL -- -- ADBASE<15:1> SWTRG1 -- -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 12 ADC Data Buffer13 -- -- -- -- -- IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> -- -- -- -- -- IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> -- -- -- -- -- -- P6RDY -- -- -- P2RDY -- -- -- -- -- -- -- PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 P1RDY P0RDY -- SLOWCLK -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0003 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- ADPCFG 0302 -- -- DS70318D-page 62 Bit 13 ADSIDL -- -- ADBASE<15:1> SWTRG1 SWTRG3 TRGSRC3<4:0> TRGSRC1<4:0> IRQEN0 IRQEN2 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 PEND0 PEND2 SWTRG0 SWTRG2 TRGSRC0<4:0> TRGSRC2<4:0> -- -- -- -- -- -- -- -- -- -- -- PCFG7 SLOWCLK -- GSWTRG -- FORM EIE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 ORDER PCFG6 -- Bit 5 Bit 4 SEQSAMP ASYNCSAMP PCFG5 -- PCFG4 -- Bit 3 -- PCFG3 P3RDY Bit 2 Bit 1 ADCS<2:0> PCFG2 P2RDY PCFG1 PCFG0 P1RDY P0RDY -- Bit 0 All Resets 0003 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C -- -- ADCPC3 0310 -- -- ADCBUF0 0320 ADCBUF1 0322 ADCBUF2 0324 ADCBUF3 0326 ADCBUF4 0328 ADCBUF5 032A ADCBUF12 0338 ADCBUF13 033A Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary TABLE 4-28: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- ADPCFG 0302 -- -- ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C IRQEN3 PEND3 ADCBUF0 0320 ADCBUF1 0322 ADCBUF2 0324 ADCBUF3 0326 ADCBUF4 0328 ADCBUF5 032A ADCBUF6 032C ADCBUF7 032E (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-29: Bit 13 ADSIDL -- -- ADBASE<15:1> SWTRG1 SWTRG3 -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 12 ADC Data Buffer 13 -- -- -- -- -- IRQEN6 PEND6 SWTRG6 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> TRGSRC2<4:0> TRGSRC6<4:0> -- -- -- -- -- -- P6RDY -- -- P3RDY P2RDY -- -- -- -- -- PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 SLOWCLK -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> PCFG1 PCFG0 P1RDY P0RDY -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY All Resets 0003 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- ADPCFG 0302 -- -- ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C IRQEN3 PEND3 (c) 2009 Microchip Technology Inc. ADCPC3 0310 -- -- ADCBUF0 0320 ADCBUF1 0322 ADCBUF2 0324 ADCBUF3 0326 ADCBUF4 0328 ADCBUF5 032A ADCBUF6 032C ADCBUF7 032E ADCBUF12 0338 ADCBUF13 033A DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70318D-page 63 TABLE 4-30: Bit 13 ADSIDL -- -- ADBASE<15:1> SWTRG1 SWTRG3 SWTRG5 -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 -- -- -- -- -- IRQEN6 PEND6 SWTRG6 TRGSRC5<4:0> IRQEN4 PEND4 SWTRG4 TRGSRC4<4:0> TRGSRC6<4:0> TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> -- -- -- -- -- -- P6RDY P5RDY P4RDY P3RDY P2RDY -- PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 P1RDY P0RDY -- SLOWCLK -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0003 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- ADPCFG 0302 -- -- DS70318D-page 64 ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C IRQEN3 PEND3 ADCPC2 030E IRQEN5 PEND5 ADCPC3 0310 -- -- ADCBUF0 0320 ADCBUF1 0322 ADCBUF2 0324 ADCBUF3 0326 ADCBUF4 0328 ADCBUF5 032A ADCBUF6 032C ADCBUF7 032E ADCBUF8 0330 ADCBUF9 0332 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary ADCBUF10 0334 ADCBUF11 0336 ADCBUF12 0338 ADCBUF13 033A Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. (c) 2009 Microchip Technology Inc. TABLE 4-31: Bit 14 -- -- -- -- -- -- -- -- CMREF<9:0> CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- CMPSTAT -- CMPPOL -- -- -- -- CMREF<9:0> RANGE CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- CMPSTAT -- CMPPOL RANGE Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY All Resets 0000 0000 0000 0000 File Name ADR Bit 15 CMPCON1 0540 CMPON CMPDAC1 0542 -- CMPCON2 0544 CMPON CMPDAC2 0546 -- (c) 2009 Microchip Technology Inc. Bit 14 -- -- -- -- -- -- -- -- -- -- -- -- CMPSIDL -- -- -- -- DACOE INSEL<1:0> -- -- -- CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- -- -- CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- -- -- -- CMREF<9:0> CMPSTAT -- CMPPOL RANGE CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CMPSTAT Bit 2 -- Bit 1 CMPPOL Bit 0 RANGE CMREF<9:0> -- CMPSTAT -- CMPPOL RANGE CMREF<9:0> EXTREF -- CMREF<9:0> CMPSTAT -- CMPPOL RANGE TABLE 4-32: ANALOG COMPARATOR CONTROL REGISTER MAP dsPIC33FJ16GS502/504 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 0000 0000 0000 File Name ADR Bit 15 CMPCON1 0540 CMPON CMPDAC1 0542 -- CMPCON2 0544 CMPON CMPDAC2 0546 -- CMPCON3 0548 CMPON CMPDAC3 054A -- CMPCON4 054C CMPON DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary CMPDAC4 054E -- DS70318D-page 65 TABLE 4-33: Bit 13 INT1R<5:0> -- T1CKR<5:0> T3CKR<5:0> IC2R<5:0> -- U1CTSR<5:0> SCK1R<5:0> -- FLT1R<5:0> FLT3R<5:0> FLT5R<5:0> FLT7R<5:0> SYNCI1R<5:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SS1R<5:0> -- -- -- -- -- SDI1R<5:0> -- -- U1RXR<5:0> -- -- -- -- -- -- -- OCFAR<5:0> -- -- IC1R<5:0> -- -- T2CKR<5:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT2R<5:0> -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 3F00 003F 0000 3F3F 3F3F 3F3F 003F 3F3F 0000 3F00 3F3F FLT4R<5:0> FLT6R<5:0> FLT8R<5:0> SYNCI2R<5:0> 3F3F 3F3F 3F3F 3F3F PERIPHERAL PIN SELECT INPUT REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 RPINR0 0680 -- -- RPINR1 0682 -- -- DS70318D-page 66 FLT2R<5:0> Bit 13 RP1R<5:0> RP3R<5:0> RP5R<5:0> RP7R<5:0> RP33<5:0> RP35<5:0> -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 -- -- -- -- -- -- Bit 5 Bit 4 Bit 3 Bit 2 RP0R<5:0> RP2R<5:0> RP4R<5:0> RP6R<5:0> RP32<5:0> RP34<5:0> Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 RPINR2 0684 -- -- RPINR3 0686 -- -- RPINR7 068E -- -- RPINR11 0696 -- -- RPINR18 06A4 -- -- RPINR20 06A8 -- -- RPINR21 06AA -- -- RPINR29 06BA -- -- RPINR30 06BC -- -- RPINR31 06BE -- -- RPINR32 06C0 -- -- RPINR33 06C2 -- -- RPINR34 06C4 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR DSPIC33FJ06GS101 File Name Addr Bit 15 Bit 14 RPOR0 06D0 -- -- RPOR1 06D2 -- -- RPOR2 06D4 -- -- RPOR3 06D6 -- -- RPOR16 06F0 -- -- RPOR17 06F2 -- -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-35: Bit 13 RP1R<5:0> RP3R<5:0> RP5R<5:0> RP7R<5:0> RP9R<5:0> RP11R<5:0> RP13R<5:0> RP15R<5:0> RP33<5:0> RP35<5:0> -- -- -- -- -- -- -- -- -- -- RP10R<5:0> RP12R<5:0> RP14R<5:0> RP32<5:0> RP34<5:0> -- -- RP8R<5:0> -- -- RP6R<5:0> -- -- RP4R<5:0> -- -- RP2R<5:0> -- -- RP0R<5:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND dsPIC33FJ16GS502 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name -- -- -- -- -- -- -- -- -- -- Addr Bit 15 Bit 14 RPOR0 06D0 -- RPOR1 06D2 -- RPOR2 06D4 -- RPOR3 06D6 -- RPOR4 06D8 -- (c) 2009 Microchip Technology Inc. Bit 13 RP1R<5:0> RP3R<5:0> RP5R<5:0> RP7R<5:0> RP9R<5:0> RP11R<5:0> RP13R<5:0> RP15R<5:0> RP17R<5:0> RP19R<5:0> RP21R<5:0> RP23R<5:0> RP25R<5:0> RP27R<5:0> RP29R<5:0> RP33<5:0> RP35<5:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RP0R<5:0> RP2R<5:0> RP4R<5:0> RP6R<5:0> RP8R<5:0> RP10R<5:0> RP12R<5:0> RP14R<5:0> RP16R<5:0> RP18R<5:0> RP20R<5:0> RP22R<5:0> RP24R<5:0> RP26R<5:0> RP28R<5:0> RP32<5:0> RP34<5:0> Bit 1 Bit 0 RPOR5 06DA -- RPOR6 06DC -- RPOR7 06DE -- RPOR16 06F0 -- RPOR17 06F2 -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-36: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Bit 15 Bit 14 RPOR0 06D0 -- -- RPOR1 06D2 -- -- RPOR2 06D4 -- -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary RPOR3 06D6 -- -- RPOR4 06D8 -- -- RPOR5 06DA -- -- RPOR6 06DC -- -- RPOR7 06DE -- -- RPOR8 06E0 -- -- RPOR9 06E2 -- -- RPOR10 06E4 -- -- RPOR11 06E6 -- -- RPOR12 06E8 -- -- RPOR13 06EA -- -- RPOR14 06EC -- -- RPOR16 06F0 -- -- RPOR17 06F2 -- -- DS70318D-page 67 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-37: Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- ODCA4 ODCA3 ODCA2 ODCA1 -- -- -- -- -- -- -- -- LATA4 LATA3 LATA2 LATA1 LATA0 ODCA0 -- -- -- -- -- -- -- -- RA4 RA3 RA2 RA1 RA0 -- -- -- -- -- -- -- -- TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 001F xxxx 0000 0000 PORTA REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 TRISA 02C0 -- -- PORTA 02C2 -- -- DS70318D-page 68 Bit 13 -- -- -- -- -- -- -- -- -- ODCB7 ODCB6 ODCB5 ODCB4 -- -- -- -- -- LATB7 LATB6 LATB5 LATB4 -- -- -- -- -- RB7 RB6 RB5 RB4 RB3 LATB3 ODCB3 -- -- -- -- -- TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TRISB2 RB2 LATB2 ODCB2 Bit 1 TRISB1 RB1 LATB1 ODCB1 Bit 0 TRISB0 RB0 LATB0 ODCB0 All Resets 00FF xxxx 0000 0000 Bit 13 TRISB13 RB13 LATB13 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 LATB12 LATB11 LATB10 LATB9 LATB8 RB12 RB11 RB10 RB9 RB8 RB7 LATB7 ODCB7 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TRISB6 RB6 LATB6 ODCB6 Bit 5 TRISB5 RB5 LATB5 ODCB5 Bit 4 TRISB4 RB4 LATB4 ODCB4 Bit 3 TRISB3 RB3 LATB3 ODCB3 Bit 2 TRISB2 RB2 LATB2 ODCB2 Bit 1 TRISB1 RB1 LATB1 ODCB1 Bit 0 TRISB0 RB0 LATB0 ODCB0 All Resets FFFF xxxx 0000 0000 Bit 13 TRISC13 RC13 LATC13 ODCC13 ODCC12 LATC12 LATC11 ODCC11 RC12 RC11 TRISC12 TRISC11 Bit 12 Bit 11 Bit 10 TRISC10 RC10 LATC10 ODCC10 Bit 9 TRISC9 RC9 LATC9 ODCC9 Bit 8 TRISC8 RC8 LATC8 ODCC8 Bit 7 TRISC7 RC7 LATC7 ODCC7 Bit 6 TRISC6 RC6 LATC6 ODCC6 Bit 5 TRISC5 RC5 LATC5 ODCC5 Bit 4 TRISC4 RC4 LATC4 ODCC4 Bit 3 TRISC3 RC3 LATC3 ODCC3 Bit 2 TRISC2 RC2 LATC2 ODCC2 Bit 1 TRISC1 RC1 LATC1 ODCC1 Bit 0 TRISC0 RC0 LATC0 ODCC0 All Resets 3FFF xxxx 0000 0000 LATA 02C4 -- -- ODCA 02C6 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-38: PORTB REGISTER MAP FOR DSPIC33FJ06GS101 SFR Name SFR Addr Bit 15 Bit 14 TRISB 02C8 -- -- PORTB 02CA -- -- LATB 02CC -- -- ODCB 02CE -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary TABLE 4-39: PORTB REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402, dsPIC33FJ16GS404, dsPIC33FJ16GS502 AND dsPIC33FJ16GS504 SFR Name SFR Addr Bit 15 Bit 14 TRISB 02C8 TRISB15 TRISB14 PORTB 02CA RB15 RB14 LATB 02CC LATB15 LATB14 ODCB 02CE ODCB15 ODCB14 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-40: PORTC REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504 SFR Name SFR Addr Bit 15 Bit 14 TRISC 02D0 -- -- PORTC 02D2 -- -- LATC 02D4 -- -- ODCC 02D6 -- -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-41: Bit 14 -- COSC<2:0> DOZE<2:0> -- -- TUN<5:0> APLLCK SELACLK -- -- APSTSCLR<2:0> ASRCSEL FRCSEL -- -- -- -- -- -- ROSIDL ROSEL RODIV<3:0> -- -- -- -- -- -- -- -- -- -- -- PLLDIV<8:0> -- -- DOZEN FRCDIV<2:0> PLLPOST<1:0> -- PLLPRE<4:0> -- NOSC<2:0> CLKLOCK IOLOCK LOCK -- CF -- -- -- -- -- CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR OSWEN Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYSTEM CONTROL REGISTER MAP All Resets xxxx(1) 0300(2) 3040 0030 0000 0000 0000 SFR Name SFR Addr Bit 15 RCON 0740 TRAPR IOPUWR OSCCON 0742 -- CLKDIV 0744 ROI PLLFBD 0746 -- REFOCON 074E ROON OSCTUN 0748 (c) 2009 Microchip Technology Inc. Bit 13 WRERR -- -- -- -- -- -- -- -- -- -- -- -- ERASE -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 -- NVMKEY<7:0> Bit 3 Bit 2 Bit 1 NVMOP<3:0> Bit 0 -- 0000 Bit 13 -- -- -- -- -- -- PWM4MD -- -- -- -- -- -- -- -- CMPMD -- -- -- -- IC2MD -- -- PWM1MD T2MD T1MD -- PWMMD -- IC1MD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 I2C1MD -- -- -- -- Bit 6 -- -- -- -- -- Bit 5 U1MD -- -- -- -- Bit 4 -- -- -- -- -- Bit 3 SPI1MD -- -- REFOMD -- Bit 2 -- -- -- -- -- Bit 1 -- OC2MD -- -- -- Bit 0 ADCMD OC1MD -- -- -- Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- T2MD T1MD Bit 12 Bit 11 Bit 10 -- -- CMPMD -- -- Bit 9 PWMMD IC2MD -- -- PWM2MD Bit 8 -- IC1MD -- -- PWM1MD Bit 7 I2C1MD -- -- -- -- Bit 6 -- -- -- -- -- Bit 5 U1MD -- -- -- -- Bit 4 -- -- -- -- -- Bit 3 SPI1MD -- -- REFOMD -- Bit 2 -- -- -- -- -- Bit 1 -- OC2MD -- -- -- Bit 0 ADCMD OC1MD -- -- -- ACLKCON 0750 ENAPLL Legend: Note 1: 2: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The RCON register Reset values are dependent on type of Reset. The OSCCON register Reset values are dependent on the FOSC Configuration bits and on type of Reset. TABLE 4-42: NVM REGISTER MAP All Resets 0000(1) File Name Addr Bit 15 Bit 14 NVMCON 0760 WR WREN NVMKEY 0766 -- Legend: Note 1: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary TABLE 4-43: PMD REGISTER MAP FOR DSPIC33FJ06GS101 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 -- -- PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-44: PMD REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY All Resets 0000 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 -- -- PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- DS70318D-page 69 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-45: Bit 13 -- -- -- -- -- -- -- -- -- CMP2MD CMP1MD -- -- -- -- -- -- -- -- -- PWM2MD PWM1MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- REFOMD -- -- -- -- CMPMD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC1MD -- -- -- -- -- -- -- OC1MD T2MD T1MD -- PWMMD -- I2C1MD -- U1MD -- SPI1MD -- -- ADCMD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 PMD REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 -- -- PMD2 0772 -- -- DS70318D-page 70 Bit 13 T3MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- PWM3MD PWM2MD PWM1MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC2MD IC1MD -- -- -- -- -- -- -- -- T2MD T1MD -- PWMMD -- I2C1MD -- U1MD -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SPI1MD -- -- REFOMD -- -- Bit 2 -- -- -- -- -- -- Bit 1 -- OC2MD -- -- -- -- Bit 0 ADCMD OC1MD -- -- -- -- All Resets 0000 0000 0000 0000 0000 0000 Bit 13 T3MD -- -- -- -- -- -- CMP4MD CMP3MD -- PWM4MD PWM3MD -- -- -- -- PWM2MD CMP2MD -- -- CMPMD -- -- -- -- IC2MD T2MD T1MD -- PWMMD -- IC1MD -- -- PWM1MD CMP1MD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 I2C1MD -- -- -- -- -- Bit 6 -- -- -- -- -- -- Bit 5 U1MD -- -- -- -- -- Bit 4 -- -- -- -- -- -- Bit 3 SPI1MD -- -- REFOMD -- -- Bit 2 -- -- -- -- -- -- Bit 1 -- OC2MD -- -- -- -- Bit 0 ADCMD OC1MD -- -- -- -- All Resets 0000 0000 0000 0000 0000 0000 PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- PMD7 077C -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-46: PMD REGISTER MAP FOR dsPIC33FJ16GS402 AND dsPIC33FJ16GS404 DEVICES ONLY SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 -- -- PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- PMD7 077C -- -- DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-47: PMD REGISTER MAP FOR dsPIC33FJ16GS502 AND dsPIC33FJ16GS504 DEVICES ONLY SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 -- -- PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- PMD7 077C -- -- (c) 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.6 SOFTWARE STACK 4.3 Instruction Addressing Modes In addition to its use as a working register, the W15 register in the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The addressing modes shown in Table 4-48 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.3.1 FILE REGISTER INSTRUCTIONS The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1000 in RAM, initialize the SPLIM with the value 0x0FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 FIGURE 4-6: 0x0000 15 CALL STACK FRAME 0 Stack Grows Toward Higher Address PC<15:0> 000000000 PC<22:16> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 71 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS 4.3.4 MAC INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (register offset) field is shared by both source and destination (but typically only used by one). The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by move and accumulator instructions: * * * * * * * * Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-Bit Literal 16-Bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. In summary, the following addressing modes are supported by the MAC class of instructions: * * * * * Register Indirect Register Indirect Post-Modified by 2 Register Indirect Post-Modified by 4 Register Indirect Post-Modified by 6 Register Indirect with Register Offset (Indexed) 4.3.5 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS70318D-page 72 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4 Modulo Addressing Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.4.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that will operate with Modulo Addressing: * If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled. * If YWM = 15, Y AGU Modulo Addressing is disabled. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than `15' and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than `15' and the YMODEN bit is set at MODCON<14>. 4.4.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1). FIGURE 4-7: Byte Address 0x1100 MODULO ADDRESSING OPERATION EXAMPLE MOV MOV MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON #0x0000, W0 #0x1110, W1 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;W0 holds buffer fill value ;point W1 to buffer ;fill the 50 buffer locations ;fill the next location ;increment the fill value 0x1163 DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 73 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4.3 MODULO ADDRESSING APPLICABILITY If the length of a bit-reversed buffer is M = 2N bytes, the last `N' bits of the data buffer start address must be zeros. XB<14:0> is the Bit-Reversed Address modifier, or `pivot point,' which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: * The upper boundary addresses for incrementing buffers * The lower boundary addresses for decrementing buffers It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly. Note: The modulo corrected effective address is written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7 + W2]) is used, Modulo Addressing correction is performed but the contents of the register remain unchanged. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU; Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. 4.5 Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer. Bit-Reversed Addressing mode is enabled in any of these situations: * BWM bits (W register selection) in the MODCON register are any value other than 15 (the stack cannot be accessed using Bit-Reversed Addressing) * The BREN bit is set in the XBREV register * The addressing mode used is Register Indirect with Pre-Increment or Post-Increment DS70318D-page 74 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Decimal 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 75 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6 Interfacing Program and Data Memory Spaces 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility Register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 4-50 and Figure 4-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the DSPIC33FJ06GS101/ X02 and dsPIC33FJ16GSX02/X04 architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-50: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address <23> 0 TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx 0 0 PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> 0xx xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70318D-page 76 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits EA 0 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as `0' to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 77 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is `1'; the lower byte is selected when it is `0'. * TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom byte', will always be `0'. - In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruction. The data is always `0' when the upper `phantom' byte is selected (Byte Select = 1). Similarly, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. * TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). FIGURE 4-10: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 02 23 15 0 0x000000 00000000 23 00000000 00000000 00000000 16 8 0 0x020000 0x030000 `Phantom' Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W 0x800000 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. DS70318D-page 78 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is `1' and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 4-11), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data, to execute in a single cycle. FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA<14:0> 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 79 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 80 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 5. "Flash Programming" (DS70191), which is available from the Microchip web site (www.microchip.com). signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data, either in blocks or `rows' of 64 instructions (192 bytes) at a time, or a single program memory word, and erase program memory in blocks or `pages' of 512 instructions (1536 bytes) at a time. 5.1 The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: * In-Circuit Serial ProgrammingTM (ICSPTM) programming capability * Run-Time Self-Programming (RTSP) ICSP allows a DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx, and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 81 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.2 RTSP Operation 5.3 Programming Operations The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tuning register (see Register 8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 24-12). EQUATION 5-1: PROGRAMMING TIME T ------------------------------------------------------------------------------------------------------------------------7.37 MHz x ( FRC Accuracy )% x ( FRC Tuning )% For example, if the device is operating at +125C, the FRC accuracy will be 5%. If the TUN<5:0> bits (see Register 8-4) are set to `b111111, the Minimum Row Write Time is: 11064 Cycles T RW = ---------------------------------------------------------------------------------------------- = 1.435ms 7.37 MHz x ( 1 + 0.05 ) x ( 1 - 0.00375 ) and, the Maximum Row Write Time is: 11064 Cycles T RW = --------------------------------------------------------------------------------------------- = 1.586ms 7.37 MHz x ( 1 - 0.05 ) x ( 1 - 0.00375 ) Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 "Programming Operations" for further details. DS70318D-page 82 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-1: R/SO-0(1) WR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable Only bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 -- U-0 -- R/W-0(1) R/W-0(1) R/W-0(1) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WREN R/W-0(1) WRERR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0(1) bit 0 NVMOP<3:0>(2) WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as `0' ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command Unimplemented: Read as `0' NVMOP<3:0>: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase general segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 83 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-2: U-0 -- bit 15 W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown W-0 W-0 W-0 W-0 W-0 W-0 W-0 bit 0 NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 NVMKEY<7:0> Unimplemented: Read as `0' NVMKEY<7:0>: Key Register bits (write-only) DS70318D-page 84 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. One row of program Flash memory can be programmed at a time. To achieve this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 85 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch * * * ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: DISI MOV MOV MOV MOV BSET NOP NOP #5 INITIATING A PROGRAMMING SEQUENCE ; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR DS70318D-page 86 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.0 Note: RESETS This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 8. "Reset" (DS70192), which is available from the Microchip web site (www.microchip.com). Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected. Note: Refer to the specific peripheral section or Section 3.0 "CPU" of this data sheet for register Reset states. All types of device Reset sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR clears all the bits, except for the POR bit (RCON<0>), that are set. The user application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset is meaningful. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * * POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Pin Reset SWR: Software RESET Instruction WDTO: Watchdog Timer Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset A simplified block diagram of the Reset module is shown in Figure 6-1. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR SYSRST POR VDD Internal Regulator VDD Rise Detect Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 87 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR RCON: RESET CONTROL REGISTER(1) R/W-0 IOPUWR U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CM R/W-0 VREGS bit 8 R/W-1 POR bit 0 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has NOT occurred VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep EXTR: External Reset Pin (MCLR) bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset Flag (Instruction) bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70318D-page 88 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 6-1: bit 1 RCON: RESET CONTROL REGISTER(1) (CONTINUED) BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred bit 0 Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 89 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.1 System Reset 2. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures that the voltage regulator output becomes stable. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT, has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to Section 8.0 "Oscillator Configuration" for more information. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay, TFSCM, elapsed. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 families of devices have two types of Reset: * Cold Reset * Warm Reset A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR). On a cold Reset, the FNOSC Configuration bits in the FOSC Configuration register select the device clock source. A warm Reset is the result of all the other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register. The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is detailed below and is shown in Figure 6-2. 1. POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. 3. 4. 5. 6. TABLE 6-1: OSCILLATOR DELAY Oscillator Startup Delay TOSCD(1) TOSCD(1) TOSCD(1) TOSCD(1) -- TOSCD(1) TOSCD(1) -- TOSCD(1) Oscillator Startup Timer -- -- TOST(2) TOST(2) -- TOST(2) TOST(2) -- -- PLL Lock Time -- TLOCK(3) -- -- -- TLOCK(3) TLOCK(3) TLOCK(3) -- Total Delay TOSCD(1) TOSCD + TLOCK(1,3) TOSCD + TOST(1,2) TOSCD + TOST(1,2) -- TOSCD + TOST + TLOCK(1,2,3) TOSCD + TOST + TLOCK(1,2,3) TLOCK(3) TOSCD(1) Oscillator Mode FRC, FRCDIV16, FRCDIVN FRCPLL XT HS EC XTPLL HSPLL ECPLL LPRC Note 1: 2: 3: TOSCD = Oscillator start-up delay (1.1 s max for FRC, 70 s max for LPRC). Crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. TOST = Oscillator start-up timer delay (1024 oscillator clock period). For example, TOST = 102.4 s for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal. TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled. DS70318D-page 90 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR POR Reset 1 TBOR 2 BOR Reset 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 FSCM 5 Device Status Reset Run TFSCM Time Note 1: 2: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to Section 8.0 "Oscillator Configuration" for more information. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, TFSCM, has elapsed. 3: 4: 5: 6: (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 91 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 6-2: VPOR TPOR VBOR TBOR TPWRT TFSCM OSCILLATOR DELAY Symbol Parameter POR threshold POR extension time BOR threshold BOR extension time Programmable power-up time delay Fail-Safe Clock Monitor delay 1.8V nominal 30 s maximum 2.5V nominal 100 s maximum 0-128 ms nominal 900 s maximum Value Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST becomes inactive, is long enough to get all operating parameters within specification. 6.2.1 Brown-out Reset (BOR) and Power-up Timer (PWRT) The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD is too low (VDD < VBOR) for proper device operation. The BOR circuit keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. The BOR status (BOR) bit in the Reset Control (RCON<1>) register is set to indicate the Brown-out Reset. The device will not run at full speed after a BOR as the VDD should rise to acceptable levels for full-speed operation. The PWRT provides power-up time delay (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the SYSRST is released. The power-up timer delay (TPWRT) is programmed by the Power-on Reset Timer Value Select (FPWRT<2:0>) bits in the POR Configuration (FPOR<2:0>) register, which provides eight settings (from 0 ms to 128 ms). Refer to Section 21.0 "Special Features" for further details. Figure 6-3 shows the typical brown-out scenarios. The reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point 6.2 Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 24.0 "Electrical Characteristics" for details. The POR status (POR) bit in the Reset Control (RCON<0>) register is set to indicate the Power-on Reset. DS70318D-page 92 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 6-3: VDD VBOR TBOR + TPWRT SYSRST BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD dips before PWRT expires VDD VBOR TBOR + TPWRT SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 24.0 "Electrical Characteristics" for minimum pulse width specifications. The external Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. the RESET instruction will remain. SYSRST is released at the next instruction cycle and the Reset vector fetch will commence. The Software Reset (SWR) flag (instruction) in the Reset Control (RCON<6>) register is set to indicate the software Reset. 6.5 Watchdog Time-out Reset (WDTO) 6.3.0.1 EXTERNAL SUPERVISORY CIRCUIT Many systems have external supervisory circuits that generate Reset signals to reset multiple devices in the system. This external Reset signal can be directly connected to the MCLR pin to reset the device when the rest of system is reset. Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up the processor, but will not reset the processor. The Watchdog Timer Time-out (WDTO) flag in the Reset Control (RCON<4>) register is set to indicate the Watchdog Reset. Refer to Section 21.4 "Watchdog Timer (WDT)" for more information on Watchdog Reset. 6.3.0.2 INTERNAL SUPERVISORY CIRCUIT When using the internal power supervisory circuit to reset the device, the external Reset pin (MCLR) should be tied directly or resistively to VDD. In this case, the MCLR pin will not be used to generate a Reset. The external Reset pin (MCLR) does not have an internal pull-up and must not be left unconnected. 6.6 Trap Conflict Reset 6.4 Software RESET Instruction (SWR) If a lower priority hard trap occurs while a higher priority trap is being processed, a hard Trap Conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category. The Trap Reset (TRAPR) flag in the Reset Control (RCON<15>) register is set to indicate the Trap Conflict Reset. Refer to Section 7.0 "Interrupt Controller" for more information on Trap Conflict Resets. Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 93 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.7 Configuration Mismatch Reset each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. To maintain the integrity of the Peripheral Pin Select Control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset occurs. The Configuration Mismatch (CM) flag in the Reset Control (RCON<9>) register is set to indicate the Configuration Mismatch Reset. Refer to Section 10.0 "I/O Ports" for more information on the Configuration Mismatch Reset. Note: The Configuration Mismatch Reset feature and associated Reset flag are not available on all devices. 6.8.2 UNINITIALIZED W REGISTER RESET Any attempt to use the uninitialized W register as an Address Pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. 6.8.3 SECURITY RESET If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a Security Reset. The PFC occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine or other form of branch instruction. The VFC occurs when the program counter is reloaded with an interrupt or trap vector. Refer to Section 21.8 "Code Protection and CodeGuardTM Security" for more information on Security Reset. 6.8 Illegal Condition Device Reset An illegal condition device Reset occurs due to the following sources: * Illegal Opcode Reset * Uninitialized W Register Reset * Security Reset The Illegal Opcode or Uninitialized W Access Reset (IOPUWR) flag in the Reset Control (RCON<14>) register is set to indicate the illegal condition device Reset. 6.9 Using the RCON Status Bits 6.8.1 ILLEGAL OPCODE RESET A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Table 6-3 provides a summary of the Reset flag bit operation. TABLE 6-3: Flag Bit RESET FLAG BIT OPERATION Set by: Trap conflict event Illegal opcode or uninitialized W register access or Security Reset Configuration Mismatch MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR Cleared by: TRAPR (RCON<15>) IOPWR (RCON<14>) CM (RCON<9>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits can be set or cleared by user software. DS70318D-page 94 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 41. "Interrupts (Part IV)" (DS70300), which is available on the Microchip web site (www.microchip.com). 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU. It has the following features: * Up to eight processor exceptions and software traps * Seven user-selectable priority levels * Interrupt Vector Table (IVT) with up to 118 vectors * A unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies 7.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of eight nonmaskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement up to 35 unique interrupts and 4 non-maskable traps. These are summarized in Table 7-1. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 95 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 7-1: DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR TABLE Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Start of Code 0x000000 0x000002 0x000004 0x000014 Decreasing Natural Order Priority 0x00007C 0x00007E 0x000080 Interrupt Vector Table (IVT)(1) 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70318D-page 96 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 7-1: Vector Number INTERRUPT VECTORS Interrupt Request (IQR) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30-56 57 58-64 65 66-93 94 95 96 97 98 99 100 101 102 103 IVT Address AIVT Address Interrupt Source 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38-64 65 66-72 73 74-101 102 103 104 105 106 107 108 109 110 111 Highest Natural Order Priority 0x000014 0x000114 INT0 - External Interrupt 0 0x000016 0x000116 IC1 - Input Capture 1 0x000018 0x000118 OC1 - Output Compare 1 0x00001A 0x00011A T1 - Timer1 0x00001C 0x00011C Reserved 0x00001E 0x00011E IC2 - Input Capture 2 0x000020 0x000120 OC2 - Output Compare 2 0x000022 0x000122 T2 - Timer2 0x000024 0x000124 T3 - Timer3 0x000026 0x000126 SPI1E - SPI1 Fault 0x000028 0x000128 SPI1 - SPI1 Transfer Done 0x00002A 0x00012A U1RX - UART1 Receiver 0x00002C 0x00012C U1TX - UART1 Transmitter 0x00002E 0x00012E ADC - ADC Group Convert Done 0x000030 0x000130 Reserved 0x000032 0x000132 Reserved 0x000034 0x000134 SI2C1 - I2C1 Slave Event 0x000036 0x000136 MI2C1 - I2C1 Master Event 0x000038 0x000138 CMP1 - Analog Comparator 1 Interrupt 0x00003A 0x00013A CN - Input Change Notification Interrupt 0x00003C 0x00013C INT1 - External Interrupt 1 0x00003E 0x00013E Reserved 0x000040 0x000140 Reserved 0x000042 0x000142 Reserved 0x000044 0x000144 Reserved 0x000046 0x000146 Reserved 0x000048 0x000148 Reserved 0x00004A 0x00014A Reserved 0x00004C 0x00014C Reserved 0x00004E 0x00014E INT2 - External Interrupt 2 Reserved 0x000086 0x000186 PWM PSEM Special Event Match Reserved 0x000096 0x000196 U1E - UART1 Error Interrupt Reserved 0x0000D0 0x0001D0 PWM1 - PWM1 Interrupt 0x0000D2 0x0001D2 PWM2 - PWM2 Interrupt 0x0000D4 0x0001D4 PWM3 - PWM3 Interrupt 0x0000D6 0x0001D6 PWM4 - PWM4 Interrupt 0x0000D8 0x0001D8 Reserved 0x0000DA 0x0001DA Reserved 0x0000DC 0x0001DC Reserved 0x0000DE 0x0001DE Reserved 0x0000E0 0x0001E0 Reserved 0x0000E2 0x00001E2 CMP2 - Analog Comparator 2 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 97 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 7-1: Vector Number 112 113 114 115 116 117 118 119 120 121 122 123 124 125 INTERRUPT VECTORS (CONTINUED) Interrupt Request (IQR) 104 105 106 107 108 109 110 111 112 113 114 115 116 117 IVT Address AIVT Address Interrupt Source 0x0000E4 0x0001E4 CMP3 - Analog Comparator 3 0x0000E6 0x0001E6 CMP4 - Analog Comparator 4 0x0000E8 0x0001E8 Reserved 0x0000EA 0x0001EA Reserved 0x0000EC 0x0001EC Reserved 0x0000EE 0x0001EE Reserved 0x0000F0 0x0001F0 ADC Pair 0 Convert Done 0x0000F2 0x0001F2 ADC Pair 1 Convert Done 0x0000F4 0x0001F4 ADC Pair 2 Convert Done 0x0000F6 0x0001F6 ADC Pair 3 Convert Done 0x0000F8 0x0001F8 ADC Pair 4 Convert Done 0x0000FA 0x0001FA ADC Pair 5 Convert Done 0x0000FC 0x0001FC ADC Pair 6 Convert Done 0x0000FE 0x0001FE Reserved Lowest Natural Order Priority DS70318D-page 98 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.3 Interrupt Control and Status Registers 7.3.5 INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt priority Level, which are latched into the Vector Number (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 7-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit is found in IEC0<0> and the INT0IP bits are found in the first position of IPC0 (IPC0<2:0>). The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement 27 registers for the interrupt controller: * * * * * * INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. 7.3.6 STATUS/CONTROL REGISTERS Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. * The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt Priority Level. The user can change the current CPU priority level by writing to the IPL bits. * The CORCON register contains the IPL3 bit, which together with IPL<2:0>, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 7-1 through Register 7-35 in the following pages. 7.3.2 IFSx The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 IECx The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. 7.3.4 IPCx The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 99 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-1: R-0 OA bit 15 R/W-0(3) IPL2 bit 7 Legend: C = Clearable bit S = Settable bit `1' = Bit is set bit 7-5 R = Readable bit W = Writable bit `0' = Bit is cleared U = Unimplemented bit, read as `0' -n = Value at POR x = Bit is unknown (2) SR: CPU STATUS REGISTER(1) R-0 OB R/C-0 SA R/C-0 SB R-0 OAB R/C-0 SAB R -0 DA R/W-0 DC bit 8 R/W-0(3) IPL1 (2) R/W-0(3) IPL0 (2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register 3-1. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 3: The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: U-0 -- bit 15 R/W-0 SATA bit 7 Legend: R = Readable bit 0' = Bit is cleared bit 3 CORCON: CORE CONTROL REGISTER(1) U-0 -- U-0 -- U-0 US R/W-0 EDT R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 C = Clearable bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register 3-2. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70318D-page 100 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: R/W-0 NSTDIS bit 15 R/W-0 SFTACERR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DIV0ERR U-0 -- R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL U-0 -- bit 0 INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 OVAERR R/W-0 OVBERR R/W-0 COVAERR R/W-0 COVBERR R/W-0 OVATE R/W-0 OVBTE R/W-0 COVTE bit 8 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero Unimplemented: Read as `0' MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 101 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: bit 2 INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0' bit 1 bit 0 DS70318D-page 102 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-4: R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 INT2EP R/W-0 INT1EP INTCON2: INTERRUPT CONTROL REGISTER 2 R-0 DISI U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as `0' INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 14 bit 13-3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 103 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: U-0 -- bit 15 R/W-0 T2IF(1,2) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IF(1,2) R/W-0 IC2IF U-0 -- R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF(1) IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 -- R/W-0 ADIF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPI1EIF R/W-0 T3IF(1,2) bit 8 R/W-0 INT0IF bit 0 Unimplemented: Read as `0' ADIF: ADC Group Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit(1,2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit(1,2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit(1,2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: This bit is not implemented in DSPIC33FJ06GS101/102 devices. 2: These bits are not implemented in dsPIC33FJ06GS202 devices. DS70318D-page 104 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: bit 2 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 bit 0 Note 1: This bit is not implemented in DSPIC33FJ06GS101/102 devices. 2: These bits are not implemented in dsPIC33FJ06GS202 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 105 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT1IF R/W-0 CNIF R/W-0 AC1IF (1) IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 -- R/W-0 INT2IF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 Unimplemented: Read as `0' INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AC1IF: Analog Comparator 1 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: This bit is not implemented in dsPIC33FJ16GS402/404 and DSPIC33FJ06GS101/102 devices. DS70318D-page 106 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-7: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PSEMIF U-0 -- bit 8 Unimplemented: Read as `0' PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 8-0 REGISTER 7-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U1EIF U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 107 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-9: R/W-0 PWM2IF(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 PWM1IF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 PWM2IF: PWM2 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 14 bit 13-0 Note 1: This bit is not implemented in DSPIC33FJ06GS101/102 devices. DS70318D-page 108 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-10: R/W-0 ADCP1IF bit 15 R/W-0 AC2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (2) IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AC4IF (1,2) R/W-0 AC3IF(1,2) bit 8 ADCP0IF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PWM4IF (1,3) R/W-0 PWM3IF(4) bit 0 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' AC4IF: Analog Comparator 4 Interrupt Flag Status bit(1,2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AC3IF: Analog Comparator 3 Interrupt Flag Status bit(1,2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AC2IF: Analog Comparator 2 Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' PWM4IF: PWM4 Interrupt Flag Status bit(1,3) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM3IF: PWM3 Interrupt Flag Status bit(4) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6-2 bit 1 bit 0 Note 1: These bits are unimplemented in dsPIC33FJ06GS202 devices. 2: These bits are unimplemented in DSPIC33FJ06GS101 and dsPIC33FJ16GS502 devices. 3: These bits are unimplemented in dsPIC33FJ16GS402/404/502 devices. 4: These bits are unimplemented in dsPIC33FJ06101/102/202 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 109 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-11: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 ADCP6IF R/W-0 ADCP5IF (1) IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ADCP4IF (1) R/W-0 ADCP3IF (2) R/W-0 ADCP2IF(3) bit 0 Unimplemented: Read as `0' ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit(3) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 bit 2 bit 1 bit 0 Note 1: These bits are not implemented in DSPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/402/502 devices. 2: This bit is not implemented in dsPIC33FJ06GS102/202 devices. 3: This bit is not implemented in DSPIC33FJ06GS101 devices. DS70318D-page 110 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: U-0 -- bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IE(1,2) R/W-0 IC2IE(1,2) U-0 -- R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE(1) IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 -- R/W-0 ADIE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPI1EIE R/W-0 T3IE(1,2) bit 8 R/W-0 INT0IE bit 0 Unimplemented: Read as `0' ADIE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1EIE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit(1,2) 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit(1,2) 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit(1,2) 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: These bits are unimplemented in DSPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 111 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: bit 2 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 bit 0 Note 1: These bits are unimplemented in DSPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. DS70318D-page 112 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-13: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT1IE R/W-0 CNIE R/W-0 AC1IE (1) IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 -- R/W-0 INT2IE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 Unimplemented: Read as `0' INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled AC1IE: Analog Comparator 1 Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: This bit is not implemented in DSPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 113 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-14: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PSEMIE U-0 -- bit 8 Unimplemented: Read as `0' PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' bit 8-0 REGISTER 7-15: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U1EIE U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' bit 0 DS70318D-page 114 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-16: R/W-0 PWM2IE bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 (1) IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 PWM1IE PWM2IE: PWM2 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' bit 14 bit 13-0 Note 1: This bit is unimplemented in DSPIC33FJ06GS101/102 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 115 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-17: R/W-0 ADCP1IE bit 15 R/W-0 AC2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (2) IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AC4IE (1,2) R/W-0 AC3IE(1,2) bit 8 ADCP0IE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PWM4IE (1,3) R/W-0 PWM3IE(4) bit 0 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0 AC4IE: Analog Comparator 4 Interrupt Enable bit(1,2) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled AC3IE: Analog Comparator 3 Interrupt Enable bit(1,2) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled AC2IE: Analog Comparator 2 Interrupt Enable bit(2) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' PWM4IE: PWM4 Interrupt Enable bit(1,3) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM3IE: PWM3 Interrupt Enable bit(4) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6-2 bit 1 bit 0 Note 1: These bits are unimplemented in dsPIC33FJ06GS202 devices. 2: These bits are unimplemented in DSPIC33FJ06GS101 and dsPIC33FJ16GS502 devices. 3: These bits are unimplemented in dsPIC33FJ16GS402/404/502 devices. 4: These bits are unimplemented in dsPIC33FJ06101/102/202 devices. DS70318D-page 116 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-18: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 ADCP4IE(1) R/W-0 ADCP3IE(2) IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ADCP2IE(3) bit 0 ADCP6IE(3) ADCP5IE(1) Unimplemented: Read as `0' ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit(3) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit(2) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit(3) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit bit bit bit Note 1: These bits are not implemented in DSPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/402/502 devices. 2: This bit is not implemented in dsPIC33FJ06GS102/202 devices. 3: This bit is not implemented in DSPIC33FJ06GS101 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 117 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-19: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC1IP<2:0>(1) R/W-0 U-0 -- R/W-1 R/W-0 INT0IP<2:0> bit 0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 R/W-0 T1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 Note 1: These bits are unimplemented in DSPIC33FJ06GS101/102 devices. DS70318D-page 118 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-20: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC2IP<2:0>(1,2) R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 R/W-0 T2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC2IP<2:0>(1) bit 8 R/W-0 Unimplemented: Read as `0' T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits(1,2) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0 Note 1: These bits are not implemented in DSPIC33FJ06GS101/202 devices. 2: These bits are not implemented in dsPIC33FJ06GS102 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 119 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-21: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SPI1EIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T3IP<2:0>(1) bit 0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 R/W-0 U1RXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T3IP<2:0>: Timer3 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 Note 1: These bits are not implemented in DSPIC33FJ06GS101/102/202 devices. DS70318D-page 120 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-22: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 U1TXIP<2:0> bit 0 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 121 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-23: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 MI2C1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SI2C1IP<2:0> bit 0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 R/W-0 CNIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 AC1IP<2:0>(1) bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 Note 1: These bits are not implemented in DSPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. DS70318D-page 122 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-24: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 INT1IP<2:0> bit 0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled REGISTER 7-25: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-1 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 R/W-0 INT2IP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 3-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 123 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-26: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PSEMIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 3-0 REGISTER 7-27: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 R/W-0 U1EIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 3-0 DS70318D-page 124 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-28: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 R/W-1 R/W-0 PWM2IP(1) R/W-0 U-0 -- R/W-1 R/W-0 PWM1IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' PWM2IP<2:0>: PWM2 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11 bit 10-8 bit 7-0 Note 1: These bits are not implemented in DSPIC33FJ06GS101/102 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 125 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-29: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PWM4IP (1) IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 U-0 -- R/W-1 R/W-0 PWM3IP<2:0> (2) R/W-0 bit 0 Unimplemented: Read as `0' PWM4IP<2:0>: PWM4 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM3IP<2:0>: PWM3 Interrupt Priority bits(2) 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Note 1: These bits are not implemented in dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices. 2: These bits are not implemented in dsPIC33FJ06101/102/202 devices. DS70318D-page 126 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-30: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 R/W-1 R/W-0 AC2IP<2:0> (1) R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11-01 Note 1: These bits are not implemented in DSPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 127 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-31: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 AC4IP<2:0>(1) R/W-0 U-0 -- R/W-1 R/W-0 AC3IP<2:0>(1,2) bit 0 IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits(1,2) 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Note 1: These bits are not implemented in dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices. 2: These bits are not implemented in DSPIC33FJ06GS101/102 devices. DS70318D-page 128 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-32: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 R/W-1 R/W-0 ADCP1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP0IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11 bit 10-8 bit 7-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 129 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-33: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADCP3IP<2:0> (2,3) IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 R/W-1 R/W-0 ADCP5IP<2:0>(4) R/W-0 U-0 -- R/W-1 R/W-0 ADCP4IP<2:0>(4) bit 8 R/W-0 U-0 -- R/W-1 R/W-0 ADCP2IP<2:0> (1) R/W-0 R/W-0 bit 0 Unimplemented: Read as `0' ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits(4) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits(4) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits(2,3) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 Note 1: These bits are not implemented in DSPIC33FJ06GS101 devices. 2: These bits are not implemented in dsPIC33FJ06GS102 devices. 3: These bits are not implemented in dsPIC33FJ06GS202 devices. 4: These bits are implemented in dsPIC33FJ16GS504 devices only. DS70318D-page 130 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-34: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 ADCP6IP<2:0>(1) bit 0 IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are not implemented in dsPIC33FJ06GS202 devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 131 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-35: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 VECNUM<6:0> bit 0 R-0 R-0 R-0 INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 -- U-0 -- U-0 -- R-0 R-0 ILR<3:0> bit 8 R-0 R-0 Unimplemented: Read as `0' ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 * * * 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 Unimplemented: Read as `0' VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is number 135 * * * 0000001 = Interrupt vector pending is number 9 0000000 = Interrupt vector pending is number 8 bit 7 bit 6-0 DS70318D-page 132 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.4 7.4.1 Interrupt Setup Procedures INITIALIZATION 7.4.3 TRAP SERVICE ROUTINE Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized such that all user interrupt sources are assigned to priority level 4. A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE The following steps outline the procedure to disable all user interrupts: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value EOh with SRL. To enable user interrupts, the POP instruction can be used to restore the previous SR value. Note: Only user interrupts with a priority level of 7 or lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. 3. 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. 7.4.2 INTERRUPT SERVICE ROUTINE the the the the The method used to declare an ISR and initialize IVT with the correct vector address depends on programming language (C or assembler) and language development toolsuite used to develop application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 133 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 134 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 42. "Oscillator (Part IV)" (DS70307), which is available from the Microchip web site (www.microchip.com). The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 oscillator system provides: * External and internal oscillator options as clock sources * An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency * An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware * Clock switching between various clock sources * Programmable clock postscaler for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures * A Clock Control register (OSCCON) * Nonvolatile Configuration bits for main oscillator selection. * Auxiliary PLL for ADC and PWM A simplified diagram of the oscillator system is shown in Figure 8-1. FIGURE 8-1: DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 OSCILLATOR SYSTEM DIAGRAM DOZE<2:0> Primary Oscillator POSCCLK XT, HS, EC XTPLL, HSPLL, ECPLL, FRCPLL FVCO(1) S2 DOZE FCY OSC1 R (2) S3 S1 OSC2 POSCMD<1:0> PLL(1) S1/S3 FP /2 FRCDIV FRC Oscillator FRCCLK FRCDIVN S7 FOSC TUN<5:0> / 16 FRCDIV<2:0> FRCDIV16 FRC LPRC Oscillator LPRC S6 S0 S5 Reference Clock Generation POSCCLK FOSC /N REFCLKO RPx ROSEL Auxiliary Clock Generation POSCCLK FRCCLK APLL x16 FVCO(1) ACLK /N To PWM/ADC RODIV<3:0> Clock Fail S7 Clock Switch Reset NOSC<2:0> FNOSC<2:0> WDT, PWRT, FSCM ASRCSEL Note 1: 2: FRCSEL ENAPLL SELACLK APSTSCLR<2:0> See Section 8.1.3 "PLL Configuration" and Section 8.2 "Auxiliary Clock Generation" for FVCO values. If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 135 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1 CPU Clocking System output frequencies for device operation. PLL configuration is described in Section 8.1.3 "PLL Configuration". The FRC frequency depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tuning register (see Register 8-4). The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices provide six system clock options: * * * * * * Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler 8.1.2 SYSTEM CLOCK SELECTION 8.1.1 SYSTEM CLOCK SOURCES The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as its clock source: * XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. * HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. * EC (External Clock): The external clock signal is directly applied to the OSC1 pin. The LPRC internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase-Locked Loop (PLL) to provide a wide range of The oscillator source used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 21.1 "Configuration Bits" for further details.) The Initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection. The Configuration bits allow users to choose among 12 different clock modes, shown in Table 8-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected), FOSC, is divided by 2 to generate the device instruction clock (FCY) and the peripheral clock time base (FP). FCY defines the operating speed of the device and speeds up to 40 MHz are supported by the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 architecture. Instruction execution speed or device operating frequency, FCY, is given by Equation 8-1. EQUATION 8-1: DEVICE OPERATING FREQUENCY FCY = FOSC/2 TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> Internal Internal Internal Reserved Primary Primary Primary Primary Primary Primary Internal Internal xx xx xx xx 10 01 00 10 01 00 xx xx FNOSC<2:0> 111 110 101 100 011 011 011 010 010 010 001 000 Note 1, 2 1 1 -- -- -- 1 -- -- 1 1 1 Fast RC Oscillator with Divide-by-N (FRCDIVN) Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Reserved Primary Oscillator (HS) with PLL (HSPLL) Primary Oscillator (XT) with PLL (XTPLL) Primary Oscillator (EC) with PLL (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2: OSC2 pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS70318D-page 136 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2. The output of the primary oscillator or FRC, denoted as `FIN', is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL's Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor `N1' is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, `M', by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The VCO output is further divided by a postscale factor, `N2'. This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). `N2' can be either 2, 4, or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output `FIN', the PLL output `FOSC' is given by Equation 8-2. EQUATION 8-2: FOSC CALCULATION M ( N1*N2) FOSC = FIN * For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL (see Equation 8-3). * If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. * If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. * If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. EQUATION 8-3: FOSC 2 1 2 XT WITH PLL MODE EXAMPLE FCY = = ( 10000000 * 32 ) = 40 MIPS 2*2 FIGURE 8-2: DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL BLOCK DIAGRAM 0.8-8.0 MHz Here(1) FVCO 100-200 MHz Here(1) VCO PLLDIV N1 Divide by 2-33 M Divide by 2-513 PLLPOST 12.5-80 MHz Here(1) FOSC Source (Crystal, External Clock or Internal RC) PLLPRE X N2 Divide by 2, 4, 8 Note 1: This frequency range must be satisfied at all times. 8.2 Auxiliary Clock Generation Note: The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a PWM or ADC. Note: To achieve 1.04 ns PWM resolution, the auxiliary clock must be set up for 120 MHz. If the primary PLL is used as a source for the auxiliary clock, then the primary PLL should be configured up to a maximum operation of 30 MIPS or less. 8.3 Reference Clock Generation The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. The reference clock output logic provides the user with the ability to output a clock signal based on the system clock or the crystal oscillator on a device pin. The user application can specify a wide range of clock scaling prior to outputting the reference clock. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 137 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-1: U-0 -- bit 15 R/W-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 y = Value set from Configuration bits on POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IOLOCK R-0 LOCK U-0 -- R/C-0 CF U-0 -- U-0 -- OSCCON: OSCILLATOR CONTROL REGISTER(1) R-0 R-0 COSC<2:0> R-0 U-0 -- R/W-y R/W-y NOSC<2:0>(2) bit 8 R/W-0 OSWEN bit 0 R/W-y Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Reserved 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with divide-by-16 111 = Fast RC oscillator (FRC) with divide-by-n Unimplemented: Read as `0' NOSC<2:0>: New Oscillator Selection bits(2) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Reserved 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with divide-by-16 111 = Fast RC oscillator (FRC) with divide-by-n CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, (FOSC bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 Note 1: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillator (Part IV)" (DS70307) in the "dsPIC33F Family Reference Manual" (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70318D-page 138 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-1: bit 3 OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure Unimplemented: Read as `0' OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete bit 2-1 bit 0 Note 1: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillator (Part IV)" (DS70307) in the "dsPIC33F Family Reference Manual" (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 139 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-2: R/W-0 ROI bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U-0 -- R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 0 R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-1 DOZE<2:0> R/W-1 R/W-0 DOZEN (1) R/W-0 R/W-0 FRCDIV<2:0> R/W-0 bit 8 R/W-0 PLLPOST<1:0> ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE<2:0>: Processor Clock Reduction Select bits 000 = FCY/1 001 = FCY/2 010 = FCY/4 011 = FCY/8 (default) 100 = FCY/16 101 = FCY/32 110 = FCY/64 111 = FCY/128 DOZEN: Doze Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 000 = FRC divide by 1 (default) 001 = FRC divide by 2 010 = FRC divide by 4 011 = FRC divide by 8 100 = FRC divide by 16 101 = FRC divide by 32 110 = FRC divide by 64 111 = FRC divide by 256 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as `N2', PLL postscaler) 00 = Output/2 01 = Output/4 (default) 10 = Reserved 11 = Output/8 Unimplemented: Read as `0' PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as `N1', PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 * * * 11111 = Input/33 bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4-0 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70318D-page 140 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PLLDIV<8> bit 8 R/W-0 bit 0 PLLDIV<7:0> Unimplemented: Read as `0' PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as `M', PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 * * * 000110000 = 50 (default) * * * 111111111 = 513 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 141 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 (1) OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 bit 0 TUN<5:0> Unimplemented: Read as `0' TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) * * * 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz) * * * 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested DS70318D-page 142 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-5: R/W-0 ENAPLL bit 15 R/W-0 ASRCSEL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 FRCSEL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R-0 APLLCK R/W-0 SELACLK U-0 -- U-0 -- R/W-0 R/W-0 APSTSCLR<2:0> bit 0 U-0 -- R/W-0 ENAPLL: Auxiliary PLL Enable bit 1 = APLL is enabled 0 = APLL is disabled APLLCK: APLL Locked Status bit (read-only) 1 = Indicates that auxiliary PLL is in lock 0 = Indicates that auxiliary PLL is not in lock SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary Oscillators provides the source clock for auxiliary clock divider 0 = Primary PLL (FVCO) provides the source clock for auxiliary clock divider Unimplemented: Read as `0' APSTSCLR<2:0>: Auxiliary Clock Output Divider bits 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit 1 = Primary oscillator is the clock source 0 = No clock input is selected FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Select FRC clock for auxiliary PLL 0 = Input clock source is determined by ASRCSEL bit setting Unimplemented: Read as `0' bit 14 bit 13 bit 12-11 bit 10-8 bit 7 bit 6 bit 5-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 143 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-6: R/W-0 ROON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 -- R/W-0 ROSIDL R/W-0 ROSEL R/W-0 R/W-0 R/W-0 (1) R/W-0 bit 8 U-0 -- bit 0 RODIV<3:0> ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output enabled on REFCLK0(2) pin 0 = Reference oscillator output disabled Unimplemented: Read as `0' ROSIDL: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep 0 = Reference oscillator output is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal used as the reference clock 0 = System clock used as the reference clock RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11-8 bit 7-0 Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits. 2: This pin is remappable. Refer to Section 10.4 "Peripheral Pin Select" for more information. DS70318D-page 144 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.4 Clock Switching Operation 2. Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices have a safeguard lock built into the switch process. Note: Primary oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD<1:0> Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC status bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled). Note 1: The processor continues to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: Refer to Section 42. "Oscillator (Part IV)" (DS70307) in the "dsPIC33F Family Reference Manual" for details. 3. 4. 5. 6. 8.4.1 ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to `0'. (Refer to Section 21.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times. 8.4.2 OSCILLATOR SWITCHING SEQUENCE 8.5 Fail-Safe Clock Monitor (FSCM) To perform a clock switch, the following basic sequence is required: 1. If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. 2. 3. The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then, the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. 4. 5. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 145 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 146 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 9. "Watchdog Timer and Power-Saving Modes" (DS70196), which is available from the Microchip web site (www.microchip.com). 9.2 Instruction-Based Power-Saving Modes The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembler syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices can manage power consumption in four different ways: * * * * Clock Frequency Instruction-Based Sleep and Idle modes Software-Controlled Doze mode Selective Peripheral Control in Software Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to wake-up. 9.2.1 SLEEP MODE The following occur in Sleep mode: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor does not operate, since the system clock source is disabled. * The LPRC clock continues to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate. This includes the items such as the input change notification on the I/O ports or peripherals that use an external clock input. * Any peripheral that requires the system clock source for its operation is disabled. The device will wake-up from Sleep mode on any of these events: * Any interrupt source that is individually enabled * Any form of device Reset * A WDT time-out On wake-up from Sleep mode, the processor restarts with the same clock source that was active when Sleep mode was entered. Combinations of these methods can be used to selectively tailor an application's power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 Clock Frequency and Clock Switching The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 "Oscillator Configuration". EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX ; Put the device into SLEEP mode ; Put the device into IDLE mode PWRSAV #SLEEP_MODE PWRSAV #IDLE_MODE (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 147 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.2.2 IDLE MODE The following occur in Idle mode: * The CPU stops executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 "Peripheral Module Disable"). * If the WDT or FSCM is enabled, the LPRC also remains active. The device will wake-up from Idle mode on any of these events: * Any interrupt that is individually enabled * Any device Reset * A WDT time-out On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. Programs can use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. For example, suppose the device is operating at 20 MIPS and the CAN module has been configured for 500 kbps based on this device operating speed. If the device is placed in Doze mode with a clock frequency ratio of 1:4, the CAN module continues to communicate at the required bit rate of 500 kbps, but the CPU now starts executing instructions at a frequency of 5 MIPS. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS 9.4 Peripheral Module Disable Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode. 9.3 Doze Mode The preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. In some circumstances, this may not be practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC(R) DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. Note: If a PMD bit is set, the corresponding module is disabled after a delay of one instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). DS70318D-page 148 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-1: U-0 -- bit 15 R/W-0 I2C1MD bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 U1MD U-0 -- R/W-0 SPI1MD U-0 -- U-0 -- PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 -- R/W-0 T3MD R/W-0 T2MD R/W-0 T1MD U-0 -- R/W-0 PWMMD U-0 -- bit 8 R/W-0 ADCMD bit 0 Unimplemented: Read as `0' T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled Unimplemented: Read as `0' PWMMD: PWM Module Disable bit 1 = PWM module is disabled 0 = PWM module is enabled Unimplemented: Read as `0' I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled Unimplemented: Read as `0' U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled Unimplemented: Read as `0' SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled Unimplemented: Read as `0' ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-1 bit 0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 149 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 OC2MD PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 IC2MD R/W-0 IC1MD bit 8 R/W-0 OC1MD bit 0 Unimplemented: Read as `0' IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled Unimplemented: Read as `0' OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled bit 8 bit 7-2 bit 1 bit 0 DS70318D-page 150 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CMPMD U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' CMPMD: Analog Comparator Module Disable bit 1 = Analog comparator module is disabled 0 = Analog comparator module is enabled Unimplemented: Read as `0' bit 9-0 REGISTER 9-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R/W-0 REFOMD U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' REFOMD: Reference Clock Generator Module Disable bit 1 = Reference clock generator module is disabled 0 = Reference clock generator module is enabled Unimplemented: Read as `0' bit 2-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 151 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 -- U-0 -- U-0 -- R/W-0 PWM4MD R/W-0 PWM3MD R/W-0 PWM2MD R/W-0 PWM1MD bit 8 Unimplemented: Read as `0' PWM4MD: PWM Generator 4 Module Disable bit 1 = PWM Generator 4 module is disabled 0 = PWM Generator 4 module is enabled PWM3MD: PWM Generator 3 Module Disable bit 1 = PWM Generator 3 module is disabled 0 = PWM Generator 3 module is enabled PWM2MD: PWM Generator 2 Module Disable bit 1 = PWM Generator 2 module is disabled 0 = PWM Generator 2 module is enabled PWM1MD: PWM Generator 1 Module Disable bit 1 = PWM Generator 1 module is disabled 0 = PWM Generator 1 module is enabled Unimplemented: Read as `0' bit 10 bit 9 bit 8 bit 7-0 DS70318D-page 152 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 -- U-0 -- U-0 -- R/W-0 CMP4MD R/W-0 CMP3MD R/W-0 CMP2MD R/W-0 CMP1MD bit 8 Unimplemented: Read as `0' CMP4MD: Analog Comparator 4 Module Disable bit 1 = Analog Comparator 4 module is disabled 0 = Analog Comparator 4 module is enabled CMP3MD: Analog Comparator 3 Module Disable bit 1 = Analog Comparator 3 module is disabled 0 = Analog Comparator 3 module is enabled CMP2MD: Analog Comparator 2 Module Disable bit 1 = Analog Comparator 2 module is disabled 0 = Analog Comparator 2 module is enabled CMP1MD: Analog Comparator 1 Module Disable bit 1 = Analog Comparator 1 module is disabled 0 = Analog Comparator 1 module is enabled Unimplemented: Read as `0' bit 10 bit 9 bit 8 bit 7-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 153 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 154 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.0 Note: I/O PORTS This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 10. "I/O Ports" (DS70193), which is available on Microchip web site (www.microchip.com). peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.1 Parallel I/O (PIO) Ports Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data Output Multiplexers I/O 1 0 1 0 Output Enable PIO Module Read TRIS Output Data Data Bus WR TRIS D CK Q I/O Pin TRIS Latch D WR LAT + WR PORT CK Data Latch Q Read LAT Input Data Read PORT (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 155 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.1.1 OPEN-DRAIN CONFIGURATION 10.2.1 I/O PORT WRITE/READ TIMING In addition to the PORT, LAT and TRIS registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (for example, 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. Refer to "Pin Diagrams" for the available pins and their functionality. One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. An example is shown in Example 10-1. 10.3 Input Change Notification 10.2 Configuring Analog Port Pins The input change notification function of the I/O ports allows the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices to generate interrupt requests to the processor in response to a Change-Of-State (COS) on selected input pins. This feature can detect input Change-Of-States even in Sleep mode, when the clocks are disabled. Depending on the device pin count, up to 30 external signals (CNx pin) can be selected (enabled) for generating an interrupt request on a Change-Of-State. Four control registers are associated with the CN module. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when the push button or keypad devices are connected. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. The ADPCFG and TRIS registers control the operation of the Analog-to-Digital (A/D) port pins. The port pins that are to function as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The ADPCFG register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default. When the PORT register is read, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. EQUATION 10-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISBB PORTB, #13 PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction DS70318D-page 156 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.4 Peripheral Pin Select 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-1 through Register 10-14). Each register contains sets of 6-bit fields, with each set associated with one of the remappable peripherals. Programming a given peripheral's bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. Figure 10-2 Illustrates remappable pin selection for U1RX input. Note: For input mapping only, the Peripheral Pin Select (PPS) functionality does not have priority over the TRISx settings. Therefore, when configuring the RPx pin for input, the corresponding bit in the TRISx register must also be configured for input (i.e., set to `1'). Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins. Programmers can independently map the input and/or output of most digital peripherals to any one of these I/O pins. Peripheral pin select is performed in software, and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping, once it has been established. 10.4.1 AVAILABLE PINS The peripheral pin select feature is used with a range of up to 30 pins. The number of available pins depends on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation "RPn" in their full pin designation, where "RP" designates a remappable peripheral and "n" is the remappable pin number. FIGURE 10-2: 10.4.2 CONTROLLING PERIPHERAL PIN SELECT REMAPPABLE MUX INPUT FOR U1RX U1RXR<5:0> 0 Peripheral pin select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. RP0 1 RP1 2 RP2 U1RX Input to Peripheral 33 RP33 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 157 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer1 External Clock Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Output Compare Fault A UART1 Receive UART1 Clear To Send SPI Data Input 1 SPI Clock Input 1 SPI Slave Select Input 1 PWM Fault Input PWM1 PWM Fault Input PWM2 PWM Fault Input PWM3 PWM Fault Input PWM4 PWM Fault Input PWM5 PWM Fault Input PWM6 PWM Fault Input PWM7 PWM Fault Input PWM8 External Synchronization signal to PWM Master Time Base External Synchronization signal to PWM Master Time Base Function Name INT1 INT2 T1CK T2CK T3CK IC1 IC2 OCFA U1RX U1CTS SDI1 SCK1 SS1 FLT1 FLT2 FLT3 FLT4 FLT5 FLT6 FLT7 FLT8 SYNCI1 SYNCI2 Register RPINR0 RPINR1 RPINR2 RPINR3 RPINR3 RPINR7 RPINR7 RPINR11 RPINR18 RPINR18 RPINR20 RPINR20 RPINR21 RPINR29 RPINR30 RPINR30 RPINR31 RPINR31 RPINR32 RPINR32 RPINR33 RPINR33 RPINR34 Configuration Bits INT1R<5:0> INT2R<5:0> T1CKR<5:0> T2CKR<5:0> T3CKR<5:0> IC1R<5:0> IC2R<5:0> OCFAR<5:0> U1RXR<5:0> U1CTSR<5:0> SDI1R<5:0> SCK1R<5:0> SS1R<5:0> FLT1R<5:0> FLT2R<5:0> FLT3R<5:0> FLT4R<5:0> FLT5R<5:0> FLT6R<5:0> FLT7R<5:0> FLT8R<5:0> SYNCI1R<5:0> SYNCI2R<5:0> DS70318D-page 158 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.4.2.2 Output Mapping FIGURE 10-3: In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets of 6-bit fields, with each set associated with one RPn pin (see Register 10-15 through Register 10-31). The value of the bit field corresponds to one of the peripherals, and that peripheral's output is mapped to the pin (see Table 10-2 and Figure 10-3). The list of peripherals for output mapping also includes a null value of `00000' because of the mapping technique. This permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPORn<5:0> Default 0 3 U1RTS Output Enable 4 Output Enable U1TX Output Enable OC2 Output Enable PWM4L Output Enable 19 45 Default U1TX Output U1RTS Output 0 3 4 Output Data RPn OC2 Output PWM4L Output 19 45 TABLE 10-2: Function NULL U1TX U1RTS SDO1 SCK1 SS1 OC1 OC2 SYNCO1 REFCLKO ACMP1 ACMP2 ACMP3 ACMP4 PWM4H PWM4L OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) RPORn<5:0> 000000 000011 000100 000111 001000 001001 010010 010011 100101 100110 100111 101000 101001 101010 101100 101101 RPn tied to default port pin RPn tied to UART1 transmit RPn tied to UART1 ready to send RPn tied to SPI1 data output RPn tied to SPI1 clock output RPn tied to SPI1 slave select output RPn tied to Output Compare 1 RPn tied to Output Compare 2 RPn tied to external device synchronization signal via PWM master time base REFCLK output signal RPn tied to Analog Comparator Output 1 RPn tied to Analog Comparator Output 2 RPn tied to Analog Comparator Output 3 RPn tied to Analog Comparator Output 4 RPn tied to PWM output pins associated with PWM Generator 4 RPn tied to PWM output pins associated with PWM Generator 4 Output Name (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 159 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.4.2.3 Virtual Pins DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices support four virtual RPn pins (RP32, RP33, RP34 and RP35), which are identical in functionality to all other RPn pins, with the exception of pinouts. These four pins are internal to the devices and are not connected to a physical device pin. These pins provide a simple way for inter-peripheral connection without utilizing a physical pin. For example, the output of the analog comparator can be connected to RP32 and the PWM Fault input can be configured for RP32 as well. This configuration allows the analog comparator to trigger PWM Faults without the use of an actual physical pin on the device. Unlike the similar sequence with the oscillator's LOCK bit, IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 10.4.3.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 10.4.3 CONTROLLING CONFIGURATION CHANGES 10.4.3.3 Configuration Bit Pin Select Lock Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33F devices include three features to prevent alterations to the peripheral map: * Control register lock sequence * Continuous state monitoring * Configuration bit pin select lock 10.4.3.1 Control Register Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (FOSC<5>) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 0x46 to OSCCON<7:0>. Write 0x57 to OSCCON<7:0>. Clear (or set) IOLOCK as a single operation. Note: MPLAB(R) C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See MPLAB C30 Help files for more information. DS70318D-page 160 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.5 Peripheral Pin Select Registers Not all output remappable peripheral registers are implemented on all devices. See the register description of the specific register for further details. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices implement 34 registers for remappable peripheral configuration: * 15 Input Remappable Peripheral Registers * 19 Output Remappable Peripheral Registers Note: Input and output register values can only be changed if OSCCON REGISTER 10-1: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 INT1R<5:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' INT1R<5:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' bit 7-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 161 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 bit 0 INT2R<5:0> Unimplemented: Read as `0' INT2R<5:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 DS70318D-page 162 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 T3CKR<5:0> T2CKR<5:0> Unimplemented: Read as `0' T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 163 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 IC2R<5:0> IC1R<5:0> Unimplemented: Read as `0' IC2R<5:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 DS70318D-page 164 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 bit 0 OCFAR<5:0> Unimplemented: Read as `0' OCFAR<5:0>: Assign Output Capture A (OCFA) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 165 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 U1CTSR<5:0> U1RXR<5:0> Unimplemented: Read as `0' U1CTSR<5:0>: Assign UART1 Clear to Send (U1CTS) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' U1RXR<5:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 DS70318D-page 166 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-7: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 SCK1R<5:0> SDI1R<5:0> Unimplemented: Read as `0' SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 167 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 bit 0 SS1R<5:0> Unimplemented: Read as `0' SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 DS70318D-page 168 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-9: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 FLT1R<5:0> Unimplemented: Read as `0' FLT1R<5:0>: Assign PWM Fault Input 1 (FLT1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' bit 7-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 169 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-10: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 FLT3R<5:0> FLT2R<5:0> Unimplemented: Read as `0' FLT3R<5:0>: Assign PWM Fault Input 3 (FLT3) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' FLT2R<5:0>: Assign PWM Fault Input 2 (FLT2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 DS70318D-page 170 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-11: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 FLT5R<5:0> FLT4R<5:0> Unimplemented: Read as `0' FLT5R<5:0>: Assign PWM Fault Input 5 (FLT5) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' FLT4R<5:0>: Assign PWM Fault Input 4 (FLT4) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 171 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-12: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 FLT7R<5:0> FLT6R<5:0> Unimplemented: Read as `0' FLT7R<5:0>: Assign PWM Fault Input 7 (FLT7) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' FLT6R<5:0>: Assign PWM Fault Input 6 (FLT6) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 DS70318D-page 172 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-13: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 0 SYNCI1R<5:0> FLT8R<5:0> Unimplemented: Read as `0' SYNCI1R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 Unimplemented: Read as `0' FLT8R<5:0>: Assign PWM Fault Input 8 (FLT8) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 bit 7-6 bit 5-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 173 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-14: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 bit 0 SYNCI2R<5:0> Unimplemented: Read as `0' SYNCI2R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 * * * 00000 = Input tied to RP0 REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP1R<5:0> RP0R<5:0> Unimplemented: Read as `0' RP1R<5:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP0R<5:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 10-2 for peripheral function numbers) DS70318D-page 174 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP3R<5:0> RP2R<5:0> Unimplemented: Read as `0' RP3R<5:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP2R<5:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for peripheral function numbers) REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP5R<5:0> RP4R<5:0> Unimplemented: Read as `0' RP5R<5:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP4R<5:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 10-2 for peripheral function numbers) (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 175 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP7R<5:0> RP6R<5:0> Unimplemented: Read as `0' RP7R<5:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP6R<5:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for peripheral function numbers) REGISTER 10-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP9R<5:0> RP8R<5:0> Unimplemented: Read as `0' RP9R<5:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP8R<5:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is not implemented in the DSPIC33FJ06GS101 device. DS70318D-page 176 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP11R<5:0> RP10R<5:0> Unimplemented: Read as `0' RP11R<5:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP10R<5:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is not implemented in the DSPIC33FJ06GS101 device. REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP13R<5:0> RP12R<5:0> Unimplemented: Read as `0' RP13R<5:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP12R<5:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is not implemented in the DSPIC33FJ06GS101 device. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 177 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP15R<5:0> RP14R<5:0> Unimplemented: Read as `0' RP15R<5:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP14R<5:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is not implemented in the DSPIC33FJ06GS101 device. REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP17R<5:0> RP16R<5:0> Unimplemented: Read as `0' RP17R<5:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP16R<5:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. DS70318D-page 178 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP19R<5:0> RP18R<5:0> Unimplemented: Read as `0' RP19R<5:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP18R<5:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP21R<5:0> RP20R<5:0> Unimplemented: Read as `0' RP21R<5:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP20R<5:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 179 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP23R<5:0> RP22R<5:0> Unimplemented: Read as `0' RP23R<5:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP22R<5:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. REGISTER 10-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP25R<5:0> RP24R<5:0> Unimplemented: Read as `0' RP25R<5:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP24R<5:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. DS70318D-page 180 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-28: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP27R<5:0> RP26R<5:0> Unimplemented: Read as `0' RP27R<5:0>: Peripheral Output Function is Assigned to RP27 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP26R<5:0>: Peripheral Output Function is Assigned to RP26 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. REGISTER 10-29: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP29R<5:0> RP28R<5:0> Unimplemented: Read as `0' RP29R<5:0>: Peripheral Output Function is Assigned to RP29 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP28R<5:0>: Peripheral Output Function is Assigned to RP28 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 181 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-30: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP33R<5:0> RP32R<5:0> Unimplemented: Read as `0' RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP32R<5:0>: Peripheral Output Function is Assigned to RP32 Output Pin bits (see Table 10-2 for peripheral function numbers) REGISTER 10-31: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 RP35R<5:0> RP34R<5:0> Unimplemented: Read as `0' RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits (see Table 10-2 for peripheral function numbers) Unimplemented: Read as `0' RP34R<5:0>: Peripheral Output Function is Assigned to RP34 Output Pin bits (see Table 10-2 for peripheral function numbers) DS70318D-page 182 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 11.0 Note: TIMER1 This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 11. "Timers" (DS70205), which is available from the Microchip web site (www.microchip.com). The Timer1 module can operate in one of the following modes: * * * * Timer mode Gated Timer mode Synchronous Counter mode Asynchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, the input clock is derived from the external clock input at the T1CK pin. The Timer modes are determined by the following bits: * Timer Clock Source Control bit (TCS): T1CON<1> * Timer Synchronization Control bit (TSYNC): T1CON<2> * Timer Gate Control bit (TGATE): T1CON<6> The timer control bit settings for different operating modes are given in the Table 11-1. The Timer1 module is a 16-bit timer, which can serve as a time counter for the Real-Time Clock (RTC), or operate as a free-running interval timer/counter. The Timer1 module has the following unique features over other timers: * Can be operated from the low-power 32 kHz crystal oscillator available on the device * Can be operated in Asynchronous Counter mode from an external clock source. * The external clock input (T1CK) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler. The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in Figure 11-1. TABLE 11-1: Mode Timer Gated Timer Synchronous Counter Asynchronous Counter TIMER MODE SETTINGS TCS 0 0 1 1 TGATE 0 1 x x TSYNC x x 1 0 FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Gate Sync Falling Edge Detect 1 Set T1IF Flag 0 FCY Prescaler (/n) 10 Reset TGATE TCKPS<1:0> 1 T1CK 00 TMR1 x1 Prescaler (/n) Sync 0 Comparator Equal TSYNC TCKPS<1:0> TGATE TCS PR1 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 183 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 11-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 R/W-0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0 T1CON: TIMER1 CONTROL REGISTER U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TCKPS<1:0> TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When T1CS = 1: This bit is ignored. When T1CS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FCY) Unimplemented: Read as `0' bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS70318D-page 184 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 12.0 Note: TIMER2/3 FEATURES This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 11. "Timers" (DS70205), which is available on the Microchip web site (www.microchip.com). * External clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. Figure 12-1 shows a block diagram of the Type B timer. Timer3 is a Type C timer that offers the following major features: * A Type C timer can be concatenated with a Type B timer to form a 32-bit timer * The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed before the prescaler A block diagram of the Type C timer is shown in Figure 12-2. Note: Timer3 is not available on all devices. Timer2 is a Type B timer that offers the following major features: * A Type B timer can be concatenated with a Type C timer to form a 32-bit timer FIGURE 12-1: TYPE B TIMER BLOCK DIAGRAM (x = 2) Gate Sync Falling Edge Detect 1 Set TxIF Flag 0 FCY Prescaler (/n) TCKPS<1:0> Prescaler (/n) TxCK TCKPS<1:0> TGATE TCS PRx Sync 10 Reset TGATE 00 TMRx x1 Comparator Equal FIGURE 12-2: TYPE C TIMER BLOCK DIAGRAM (x = 3) Gate Sync Falling Edge Detect 1 Set TxIF Flag 0 FCY Prescaler (/n) TCKPS<1:0> Sync TxCK TCKPS<1:0> TGATE TCS PRx Prescaler (/n) 10 TMRx Reset TGATE 00 x1 Comparator Equal (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 185 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The Timer2/3 module can operate in one of the following modes: * Timer mode * Gated Timer mode * Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin. The timer modes are determined by the following bits: * TCS (TxCON<1>): Timer Clock Source Control bit * TGATE (TxCON<6>): Timer Gate Control bit Timer control bit settings for different operating modes are given in the Table 12-1. When configured for 32-bit operation, only the Type B Timer Control (TxCON) register bits are required for setup and control while the Type C Timer Control register bits are ignored (except the TSIDL bit). For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority control bits of the Type C timer. The interrupt control and status bits for the Type B timer are ignored during 32-bit timer operation. The Timer2 and Timer 3 that can be combined to form a 32-bit timer are listed in Table 12-2. TABLE 12-2: Timer2 32-BIT TIMER Type C Timer (msw) Timer3 Type B Timer (lsw) TABLE 12-1: Mode Timer Gated Timer TIMER MODE SETTINGS TCS 0 0 1 TGATE 0 1 x Synchronous Counter A block diagram representation of the 32-bit timer module is shown in Figure 12-3. The 32-timer module can operate in one of the following modes: * Timer mode * Gated Timer mode * Synchronous Counter mode To configure the features of Timer2/3 for 32-bit operation: 1. 2. 3. 4. Set the T32 control bit. Select the prescaler ratio for Timer2 using the TCKPS<1:0> bits. Set the Clock and Gating modes using the corresponding TCS and TGATE bits. Load the timer period value. PR3 contains the most significant word of the value, while PR2 contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE. Use the priority bits, T3IP<2:0>, to set the interrupt priority. While Timer2 controls the timer, the interrupt appears as a Timer3 interrupt. Set the corresponding TON bit. 12.1 16-Bit Operation To configure any of the timers for individual 16-bit operation: 1. 2. 3. 4. 5. Clear the T32 bit corresponding to that timer. Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON bit. 5. 6. 6. 12.2 32-Bit Operation A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. For 32-bit timer operation, the T32 control bit in the Type B Timer Control (TxCON<3>) register must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for 32-bit operation. The timer value at any point is stored in the register pair, TMR3:TMR2, which always contains the most significant word of the count, while TMR2 contains the least significant word. DS70318D-page 186 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Falling Edge Detect PRx PRy 0 1 Set TyIF Flag Comparator FCY Prescaler (/n) 10 lsw 00 TMRx(1) msw TMRy(2) Equal TGATE Reset TCKPS<1:0> Prescaler (/n) Sync x1 TxCK TCKPS<1:0> TGATE TCS TMRyHLD Data Bus <15:0> Note 1: 2: Timerx is a Type B Timer (x = 2). Timery is a Type C Timer (y = 3). (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 187 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 R/W-0 R/W-0 T32 (1) TxCON: TIMER CONTROL REGISTER (x = 2) U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R/W-0 TCS U-0 -- bit 0 TCKPS<1:0> TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode): 1 = Starts 32-bit TMRx:TMRy timer pair 0 = Stops 32-bit TMRx:TMRy timer pair When T32 = 0 (in 16-Bit Timer mode): 1 = Starts 16-bit timer 0 = Stops 16-bit timer Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode Unimplemented: Read as `0' TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value T32: 32-Bit Timerx Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form separate 16-bit timer Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS70318D-page 188 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-2: R/W-0 TON(2) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE(2) R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 TCS(2) U-0 -- bit 0 TyCON: TIMER CONTROL REGISTER (y = 3) U-0 -- R/W-0 TSIDL(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TCKPS<1:0>(2) TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timery Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(2) 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-2 bit 1 bit 0 Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits have no effect. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 189 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 190 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.0 Note: INPUT CAPTURE This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 12. "Input Capture" (DS70198), which is available on the Microchip web site (www.microchip.com). * Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin * Capture timer value on every edge (rising and falling) * Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select one of the two 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Use of input capture to provide additional sources of external interrupts The input capture module is useful in applications requiring frequency (period) and pulse measurement. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices support up to two input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM From 16-Bit Timers TMR2 TMR3 16 16 ICTMR (ICxCON<7>) 1 Prescaler Counter (1, 4, 16) ICx Pin 3 Edge Detection Logic and Clock Synchronizer ICM<2:0> (ICxCON<2:0>) Mode Select ICOV, ICBNE (ICxCON<4:3>) FIFO R/W Logic 0 ICxBUF ICxI<1:0> ICxCON Interrupt Logic System Bus Set Flag ICxIF (in IFSx Register) Note 1: An `x' in a signal, register or bit name denotes the number of the capture channel. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 191 FIFO DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.1 Input Capture Registers ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2) U-0 -- R/W-0 ICSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 ICI<1:0> R-0, HC ICOV R-0, HC ICBNE R/W-0 R/W-0 ICM<2:0> bit 0 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 REGISTER 13-1: U-0 -- bit 15 R/W-0 ICTMR bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 Unimplemented: Read as `0' ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode Unimplemented: Read as `0' ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode. Rising edge detect-only, all other control bits are not applicable. 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling). ICI<1:0> bits do not control interrupt generation for this mode. 000 = Input capture module turned off bit 12-8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 DS70318D-page 192 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.0 Note: OUTPUT COMPARE This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 13. "Output Compare" (DS70209), which is available on the Microchip web site (www.microchip.com). The state of the output pin changes when the timer value matches the Compare register value. The output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. The output compare module can also generate interrupts on compare match events. The output compare module has multiple operating modes: * * * * * * * Active-Low One-Shot mode Active-High One-Shot mode Toggle mode Delayed One-Shot mode Continuous Pulse mode PWM mode without Fault Protection PWM mode with Fault Protection The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected. FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS OCxR Output Logic 3 SQ R Output Enable OCx Comparator 0 1 16 OCTSEL 0 1 OCM<2:0> Mode Select OCFA 16 TMR2 TMR3 TMR2 Rollover TMR3 Rollover Note: An `x' in a signal, register or bit name denotes the number of the output compare channels. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 193 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Note: Refer to Section 13. "Output Compare" in the "dsPIC33F Family Reference Manual" (DS7029) for OCxR and OCxRS register restrictions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes. The user TABLE 14-1: OCM<2:0> 000 001 010 011 100 101 110 111 OUTPUT COMPARE MODES Mode Module Disabled Active-Low One-Shot Active-High One-Shot Toggle Delayed One-Shot Continuous Pulse PWM without Fault Protection PWM with Fault Protection OCx Pin Initial State Controlled by GPIO register 0 1 Current output is maintained 0 0 `0', if OCxR is zero `1', if OCxR is non-zero `0', if OCxR is zero `1', if OCxR is non-zero OCx rising edge OCx falling edge OCx rising and falling edge OCx falling edge OCx falling edge No interrupt OCFA falling edge for OC1 to OC4 OCx Interrupt Generation -- FIGURE 14-2: OUTPUT COMPARE OPERATION Output Compare Mode Enabled Timer is Reset on Period Match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse (OCM = 101) PWM (OCM = 110 or 111) DS70318D-page 194 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 14-1: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R-0, HC OCFLT R/W-0 OCTSEL R/W-0 R/W-0 OCM<2:0> bit 0 OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 -- R/W-0 OCSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode Unimplemented: Read as `0' OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled bit 12-5 bit 4 bit 3 bit 2-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 195 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 196 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.0 Note: HIGH-SPEED PWM This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 43. "High- Speed PWM" (DS70323), which is available on the Microchip web site (www.microchip.com). Dual trigger from PWM to ADC PWMxH, PWMxL output pin swapping PWM4H, PWM4L pins remappable On-the-fly PWM frequency, duty cycle and phase shift changes * Disabling of Individual PWM generators to reduce power consumption * Leading-Edge Blanking (LEB) functionality Note: Duty cycle, dead-time, phase shift and frequency resolution is 8.32 ns in Center-Aligned PWM mode. * * * * The high-speed PWM module on the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices supports a wide variety of PWM modes and output formats. This PWM module is ideal for power conversion applications, such as: * * * * * * * AC/DC Converters DC/DC Converters Power Factor Correction(PFC) Uninterruptible Power Supply (UPS) Inverters Battery Chargers Digital Lighting Figure 15-1 conceptualizes the PWM module in a simplified block diagram. Figure 15-2 illustrates how the module hardware is partitioned for each PWM output pair for the Complementary PWM mode. Each functional unit of the PWM module is discussed in subsequent sections. The PWM module contains four PWM generators. The module has up to eight PWM output pins: PWM1H, PWM1L, PWM2H, PWM2L, PWM3H, PWM3L, PWM4H and PWM4L. For complementary outputs, these eight I/O pins are grouped into H/L pairs. 15.2 Feature Description 15.1 Features Overview The PWM module is designed for applications that require: * High-resolution at high PWM frequencies * The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode, and Push-Pull mode outputs * The ability to create multiphase PWM outputs For Center-Aligned mode, the duty cycle, period phase and dead-time resolutions will be 8 ns. Two common, medium power converter topologies are push-pull and half-bridge. These designs require the PWM output signal to be switched between alternate pins, as provided by the Push-Pull PWM mode. Phase-shifted PWM describes the situation where each PWM generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. Multiphase PWM is often used to improve DC/DC converter load transient response, and reduce the size of output filter capacitors and inductors. Multiple DC/DC converters are often operated in parallel, but phase-shifted in time. A single PWM output operating at 250 kHz has a period of 4 s, but an array of four PWM channels, staggered by 1 s each, yields an effective switching frequency of 1 MHz. Multiphase PWM applications typically use a fixed-phase relationship. Variable phase PWM is useful in Zero Voltage Transition (ZVT) power converters. Here, the PWM duty cycle is always 50%, and the power flow is controlled by varying the relative phase shift between the two PWM generators. The high-speed PWM module incorporates the following features: * 2-4 PWM generators with 4-8 outputs * Individual time base and duty cycle for each of the eight PWM outputs * Dead time for rising and falling edges: * Duty cycle resolution of 1.04 ns at 40 MIPS * Dead-time resolution of 1.04 ns at 40 MIPS * Phase shift resolution of 1.04 ns at 40 MIPS * Frequency resolution of 1.04 ns at 40 MIPS * PWM modes supported: - Standard Edge-Aligned - True Independent Output - Complementary - Center-Aligned - Push-Pull - Multiphase - Variable Phase - Fixed Off-Time - Current Reset - Current-Limit * Independent Fault/Current-Limit inputs for each of the eight PWM outputs * Output override control * Special Event Trigger * PWM capture feature * Prescaler for input clock (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 197 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM PWMCONx LEBCONx TRGCONx ALTDTRx, DTRx PTCON Pin and Mode Control Control for Blanking External Input Signals ADC Trigger Control Dead-Time Control PWM Enable and Mode Control MDC PDC1 MUX Latch Comparator Timer Phase PDC2 MUX Latch 16-bit Data Bus Comparator Timer Phase PDC3 MUX Latch Comparator Timer Phase PDC4 MUX Latch Comparator Timer Phase PTPER Timer Period Master Time Base External Time Base Synchronization Special Event Postscaler Special Event Comparison Value Pin Override Control Fault Mode and Pin Control Special Event Trigger Fault Control Logic FLTX(1) SYNCO(1) SYNCIX(1) Channel 4 Dead-Time Generator PWM4H(1) PWM4L(1) PWM GEN 4 PWM GEN 3 PWM GEN 2 PWM User, Current-Limit and Fault Override and Routing Logic PWM GEN 1 Channel 1 Dead-Time Generator PWM1H PWM1L Master Duty Cycle Register Channel 2 Dead-Time Generator Fault CLMT Override Logic PWM2H PWM2L Channel 3 Dead-Time Generator PWM3H PWM3L PTMR Comparator SEVTCMP IOCONx FCLCONx Note 1: These pins are remappable. DS70318D-page 198 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE Phase Offset TMR < PDC Timer/Counter PWM Override Logic Duty Cycle Comparator M U X PWMXL M U X Dead-Time Logic PWMXH PWM Duty Cycle Register Channel Override Values Fault Override Values Fault Active Fault Pin Fault Pin Assignment Logic 15.3 Control Registers The following registers control the operation of the high-speed PWM module. * * * * * * * * PTCON: PWM Time Base Control Register PTCON2: PWM Clock Divider Select Register PTPER: PWM Master Time Base Register(1) SEVTCMP: PWM Special Event Compare Register MDC: PWM Master Duty Cycle Register PWMCONx: PWMx Control Register PDCx: PWMx Generator Duty Cycle Register PHASEx: PWMx Primary Phase Shift Register (PHASEx Register provides the local time base period for PWMxH) DTRx: PWMx Dead-Time Register ALTDTRx: PWMx Alternate Dead-Time Register * * * SDCx: PWMx Secondary Duty Cycle Register * SPHASEx: PWMx Secondary Phase Shift Register (Provides the local time base for PWMxL) * TRGCONx: PWMx Trigger Control Register * IOCONx: PWMx I/O Control Register * FCLCONx: PWMx Fault Current-Limit Control Register * TRIGx: PWMx Primary Trigger Compare Value Register * STRIGx: PWMx Secondary Trigger Compare Value Register * LEBCONx: Leading-Edge Blanking Control Register * PWMCAPx: Primary PWMx Time Base Capture Register (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 199 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-1: R/W-0 PTEN bit 15 R/W-0 SYNCEN bit 7 (1) PTCON: PWM TIME BASE CONTROL REGISTER U-0 -- R/W-0 PTSIDL HS/HC-0 SESTAT R/W-0 SEIEN R/W-0 EIPU(1) R/W-0 R/W-0 SYNCPOL(1) SYNCOEN(1) bit 8 R/W-0 (1) U-0 -- R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 bit 0 SYNCSRC<1:0> SEVTPS<3:0> Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5-4 bit 3-0 PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled Unimplemented: Read as `0' PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode SESTAT: Special Event Interrupt Status bit 1 = Special event interrupt is pending 0 = Special event interrupt is not pending SEIEN: Special Event Interrupt Enable bit 1 = Special event interrupt is enabled 0 = Special event interrupt is disabled EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries SYNCPOL: Synchronization Input/Output Polarity bit(1) 1 = SYNCIx and SYNCO polarity is inverted (active-low) 0 = SYNCIx and SYNCO are active-high SYNCOEN: Primary Time Base Sync Enable bit(1) 1 = SYNCO output is enabled 0 = SYNCO output is disabled SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled Unimplemented: Read as `0' SYNCSRC<1:0>: Synchronous Source Selection bits(1) 00 = SYNCI1 01 = SYNCI2 10 = Reserved 11 = Reserved SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event 0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event * * * 1111 = 1:16 Postscaler generates a Special Event Trigger trigger on every sixteenth compare match event Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. DS70318D-page 200 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 0 PTCON2: PWM CLOCK DIVIDER SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 000 = Divide by 1, maximum PWM timing resolution (power-on default) 001 = Divide by 2, maximum PWM timing resolution 010 = Divide by 4, maximum PWM timing resolution 011 = Divide by 8, maximum PWM timing resolution 100 = Divide by 16, maximum PWM timing resolution 101 = Divide by 32, maximum PWM timing resolution 110 = Divide by 64, maximum PWM timing resolution 111 = Reserved Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. REGISTER 15-3: R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 PTPER: PWM MASTER TIME BASE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 bit 0 PTPER <15:8> PTPER <7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PTPER<15:0>: PWM Master Time Base (PMTMR) Period Value bits Note 1: The minimum value that can be loaded into the PTPER register is 0x0010 and the maximum value is 0xFFF8. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 201 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-4: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 SEVTCMP <7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 SEVTCMP <15:8> SEVTCMP<15:3>: Special Event Compare Count Value bits Unimplemented: Read as `0' REGISTER 15-5: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 MDC: PWM MASTER DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 MDC<15:8> MDC<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MDC<15:0>: Master PWM Duty Cycle Value bits Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of Period - 0x0008. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSB. DS70318D-page 202 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: HS/HC-0 FLTSTAT bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 U-0 -- U-0 -- U-0 -- R/W-0 CAM (2,3) (1) PWMCONx: PWMx CONTROL REGISTER HS/HC-0 TRGSTAT R/W-0 FLTIEN R/W-0 CLIEN R/W-0 TRGIEN R/W-0 ITB (3) HS/HC-0 CLSTAT (1) R/W-0 MDCS(3) bit 8 R/W-0 XPRES (4) R/W-0 IUE bit 0 DTC<1:0> FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending. This bit is cleared by setting FLTIEN = 0. CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending. This bit is cleared by setting CLIEN = 0. TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending. This bit is cleared by setting TRGIEN = 0. FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and the FLTSTAT bit is cleared CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt enabled 0 = Current-limit interrupt disabled and the CLSTAT bit is cleared TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared ITB: Independent Time Base Mode bit(3) 1 = PHASEx/SPHASEx register provides time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator MDCS: Master Duty Cycle Register Select bit(3) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx/SDCx register provides duty cycle information for this PWM generator DTC<1:0>: Dead-Time Control bits 00 = Positive dead time actively applied for all output modes 01 = Negative dead time actively applied for all output modes 10 = Dead-time function is disabled 11 = Reserved Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-6 bit 5-3 Note 1: Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller. 2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 4: To operate in External Period Reset mode, configure FCLCONx (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 203 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: bit 2 PWMCONx: PWMx CONTROL REGISTER (CONTINUED) CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Center-Aligned mode is disabled XPRES: External PWM Reset Control bit(4) 1 = Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base bit 1 bit 0 Note 1: Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller. 2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 4: To operate in External Period Reset mode, configure FCLCONx DS70318D-page 204 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-7: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx: PWMx GENERATOR DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PDCx<15:8> PDCx<7:0> PDCx<15:0>: PWM Generator # Duty Cycle Value bits Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and PWMxL. The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of 0xFFEF. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSB. REGISTER 15-8: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 SDCx: PWMx SECONDARY DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 SDCx<15:8> SDCx<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SDCx<15:0>: Secondary Duty Cycle for PWMxL Output Pin bits Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle. The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of 0xFFEF. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSB. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 205 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-9: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx: PWMx PRIMARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PHASEx<15:8> PHASEx<7:0> PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period for this PWM Generator bits Note 1: If PWMCONx DS70318D-page 206 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 SPHASEx<15:8> SPHASEx<7:0> SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits (used in Independent PWM mode only) Note 1: If PWMCONx (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 207 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 . REGISTER 15-11: DTRx: PWMx DEAD-TIME REGISTER U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 DTRx<13:8> DTRx<7:0> Unimplemented: Read as `0' DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits REGISTER 15-12: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 ALTDTRx<13:8> ALTDTR <7:0> Unimplemented: Read as `0' ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits DS70318D-page 208 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 bit 15 R/W-0 DTM bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TRGDIV<3:0> U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TRGSTRT<5:0> TRGDIV<3:0>: Trigger # Output Divider bits 0000 = Trigger output for every trigger event 0001 = Trigger output for every 2nd trigger event 0010 = Trigger output for every 3rd trigger event 0011 = Trigger output for every 4th trigger event 0100 = Trigger output for every 5th trigger event 0101 = Trigger output for every 6th trigger event 0110 = Trigger output for every 7th trigger event 0111 = Trigger output for every 8th trigger event 1000 = Trigger output for every 9th trigger event 1001 = Trigger output for every 10th trigger event 1010 = Trigger output for every 11th trigger event 1011 = Trigger output for every 12th trigger event 1100 = Trigger output for every 13th trigger event 1101 = Trigger output for every 14th trigger event 1110 = Trigger output for every 15th trigger event 1111 = Trigger output for every 16th trigger event Unimplemented: Read as `0' DTM: Dual Trigger Mode bit(1) 1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger. 0 = Secondary trigger event is not combined with the primary trigger event to create the PWM trigger. Two separate PWM triggers are generated. Unimplemented: Read as `0' TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits 000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled 000001 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled 000010 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled * * * 111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled The secondary generator cannot generate PWM trigger interrupts. bit 11-8 bit 7 bit 6 bit 5-0 Note 1: (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 209 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 PENH bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWAP R/W-0 PENL R/W-0 POLH R/W-0 POLL R/W-0 R/W-0 R/W-0 OVRENH R/W-0 OVRENL bit 8 R/W-0 OSYNC bit 0 PMOD<1:0>(1) OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> PENH: PWMH Output Pin Ownership bit 1 = PWM module controls PWMxH pin 0 = GPIO module controls PWMxH pin PENL: PWML Output Pin Ownership bit 1 = PWM module controls PWMxL pin 0 = GPIO module controls PWMxL pin POLH: PWMH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high POLL: PWML Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high PMOD<1:0>: PWM # I/O Pin Mode bits(1) 00 = PWM I/O pin pair is in the Complementary Output mode 01 = PWM I/O pin pair is in the Redundant Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 11 = PWM I/O pin pair is in the True Independent Output mode OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> provides data for output on PWMxH pin 0 = PWM generator provides data for PWMxH pin OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> provides data for output on PWMxL pin 0 = PWM generator provides data for PWMxL pin OVRDAT<1:0>: Data for PWMxH and PWMxL Pins if Override is Enabled bits If OVERENH = 1 then OVRDAT<1> provides data for PWMxH. If OVERENL = 1 then OVRDAT<0> provides data for PWMxL. FLTDAT<1:0>: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits FCLCONx bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5-4 Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. DS70318D-page 210 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMODE is Enabled bits FCLCONx bit 1 bit 0 Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 211 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 IFLTMOD bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 FLTSRC<4:0>(2,3) R/W-0 R/W-0 R/W-0 FLTPOL(1) R/W-0 R/W-0 R/W-0 R/W-0 CLSRC<4:0>(2,3) R/W-0 R/W-0 R/W-0 CLPOL(1) R/W-0 CLMOD bit 8 R/W-0 bit 0 FLTMOD<1:0> IFLTMOD: Independent Fault Mode Enable bit 1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output and Fault input maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions. 0 = Normal Fault mode: Current-limit feature maps CLDAT<1:0> bits to the PWMxH and PWMxL outputs. The PWM Fault feature maps FLTDAT<1:0> to the PWMxH and PWMxL outputs. CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM # Generator bits(2,3) 00000 = Fault 1 00001 = Fault 2 00010 = Fault 3 00011 = Fault 4 00100 = Fault 5 00101 = Fault 6 00110 = Fault 7 00111 = Fault 8 01000 = Reserved * * * 11111 = Reserved bit 14-10 bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high CLMOD: Current-Limit Mode Enable bit for PWM Generator # bit 1 = Current-limit function is enabled 0 = Current-limit function is disabled bit 8 Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. DS70318D-page 212 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 00000 = Fault 1 00001 = Fault 2 00010 = Fault 3 00011 = Fault 4 00100 = Fault 5 00101 = Fault 6 00110 = Fault 7 00111 = Fault 8 01000 = Reserved * * * 11111 = Reserved bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high FLTMOD<1:0>: Fault Mode for PWM Generator # bits 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 10 = Reserved 11 = Fault input is disabled bit 1-0 Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 213 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 TRGCMP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 TRGCMP<15:8> TRGCMP<15:3>: Trigger Control Value bits When primary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. Unimplemented: Read as `0' bit 2-0 REGISTER 15-17: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 STRGCMP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 STRGCMP<15:8> STRGCMP<15:3>: Secondary Trigger Control Value bits When secondary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. Unimplemented: Read as `0' bit 2-0 DS70318D-page 214 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER R/W-0 PHR bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 LEB<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 R/W-0 PHF R/W-0 PLR R/W-0 PLF R/W-0 FLTLEBEN R/W-0 CLLEBEN R/W-0 R/W-0 bit 8 LEB<9:8> PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger LEB counter 0 = LEB ignores rising edge of PWMxH PHF: PWMH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger LEB counter 0 = LEB ignores falling edge of PWMxH PLR: PWML Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger LEB counter 0 = LEB ignores rising edge of PWMxL PLF: PWML Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger LEB counter 0 = LEB ignores falling edge of PWMxL FLTLEBEN: Fault Input LEB Enable bit 1 = Leading-edge blanking is applied to selected Fault input 0 = Leading-edge blanking is not applied to selected Fault input CLLEBEN: Current-Limit LEB Enable bit 1 = Leading-edge blanking is applied to selected current-limit input 0 = Leading-edge blanking is not applied to selected current-limit input LEB: Leading-Edge Blanking for Current-Limit and Fault Inputs bits Value is 8 nsec increments. Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-3 bit 2-0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 215 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 bit 15 R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 PWMCAP<7:3>(1,2) R-0 R-0 U-0 -- U-0 -- U-0 -- bit 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 8 PWMCAP<15:8>(1,2) PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2) The value in this register represents the captured PWM time base value when a leading edge is detected on the current-limit input. Unimplemented: Read as `0' bit 2-0 Note 1: The capture feature is only available on primary output (PWMxH). 2: This feature is active only after LEB processing on the current-limit input signal is complete. DS70318D-page 216 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 18. "Serial Peripheral Interface (SPI)" (DS70206), which is available on the Microchip web site (www.microchip.com). The SPI module consists of a 16-bit shift register, SPIxSR (where x = 1), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions. The serial interface consists of the following four pins: * * * * SDIx (Serial Data Input) SDOx (Serial Data Output) SCKx (Shift Clock Input Or Output) SSx (Active-Low Slave Select). In Master mode operation, SCK is a clock output; in Slave mode, it is a clock input. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, analog-to-digital converters and so on. The SPI module is compatible with SPI and SIOP from Motorola(R). FIGURE 16-1: SCKx SPI MODULE BLOCK DIAGRAM 1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY SSx SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock SDOx SDIx bit 0 SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 217 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-1: R/W-0 SPIEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 SPIROV U-0 -- U-0 -- U-0 -- U-0 -- R-0 SPITBF R-0 SPIRBF bit 0 SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred Unimplemented: Read as `0' SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty. Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty. Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. bit 14 bit 13 bit 12-7 bit 6 bit 5-2 bit 1 bit 0 DS70318D-page 218 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: U-0 -- bit 15 R/W-0 SSEN(3) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CKP R/W-0 MSTEN R/W-0 R/W-0 SPRE<2:0>(2) R/W-0 R/W-0 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 -- U-0 -- R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 bit 0 PPRE<1:0>(2) Unimplemented: Read as `0' DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module; pin controlled by port function CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to `0' for the Framed SPI modes (FRMEN = 1). 2: Do not set both primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 219 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: bit 4-2 SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 bit 1-0 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to `0' for the Framed SPI modes (FRMEN = 1). 2: Do not set both primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70318D-page 220 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-3: R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 FRMDLY U-0 -- bit 0 SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 FRMPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 SPIFSD FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock Unimplemented: This bit must not be set to `1' by the user application bit 14 bit 13 bit 12-2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 221 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 222 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.0 Note: INTER-INTEGRATED CIRCUIT (I2CTM) This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 19. "Inter-Integrated Circuit (I2CTM)" (DS70195), which is available on the Microchip web site (www.microchip.com). 17.2 I2C Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only. The remaining bits of the I2CSTAT are read/write: * I2CxRSR is the shift register used for shifting data internal to the module and the user application has no access to it. * I2CxRCV is the receive buffer and the register to which data bytes are written, or from which data bytes are read. * I2CxTRN is the transmit register to which bytes are written during a transmit operation. * The I2CxADD register holds the slave address. * A status bit, ADD10, indicates 10-Bit Address mode. * The I2CxBRG acts as the Baud Rate Generator (BRG) reload value. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV, and an interrupt pulse is generated. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard with a 16-bit interface. The I2C module has a 2-pin interface: * The SCLx pin is clock. * The SDAx pin is data. The I 2C module offers the following key features: * I interface supporting both Master and Slave modes of operation. * I2C Slave mode supports 7-bit and 10-bit addressing. * I2C Master mode supports 7-bit and 10-bit addressing. * I2C port allows bidirectional transfers between master and slaves. * Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). * I2C supports multi-master operation, detects bus collision and arbitrates accordingly. 2C 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7-bit and 10-bit addressing. The I2C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: * * * I2C slave operation with 7-bit addressing I2C slave operation with 10-bit addressing I2C master operation with 7-bit or 10-bit addressing For details about the communication sequence in each of these modes, refer to the "dsPIC33F Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F Family Reference Manual" chapters. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 223 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 17-1: I2CTM BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSb SDAx Address Match Read SCLx Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic Write I2CxSTAT Read Write Collision Detect I2CxCON Read Acknowledge Generation Clock Stretching Write I2CxTRN LSb Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter TCY/2 DS70318D-page 224 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared HC = Hardware Clearable bit x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0, HC ACKEN R/W-0, HC RCEN R/W-0, HC PEN R/W-0, HC RSEN I2CxCON: I2Cx CONTROL REGISTER U-0 -- R/W-0 I2CSIDL R/W-1, HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0, HC SEN bit 0 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C pins are controlled by port functions. Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses acknowledged 0 = IPMI mode disabled A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMbus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMbus specification 0 = Disable SMbus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 225 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: bit 5 I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress bit 4 bit 3 bit 2 bit 1 bit 0 DS70318D-page 226 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: R-0, HSC ACKSTAT bit 15 R/C-0, HS IWCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared HSC = Hardware Settable/Clearable x = Bit is unknown R/C-0, HS I2COV R-0, HSC D_A R/C-0, HSC R/C-0, HSC P S R-0, HSC R_W R-0, HSC RBF I2CxSTAT: I2Cx STATUS REGISTER U-0 -- U-0 -- U-0 -- R/C-0, HSC BCL R-0, HSC GCSTAT R-0, HSC ADD10 bit 8 R-0, HSC TBF bit 0 R-0, HSC TRSTAT ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 227 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: bit 3 I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. bit 2 bit 1 bit 0 DS70318D-page 228 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 R/W-0 bit 0 AMSK<9:8> AMSK<7:0> Unimplemented: Read as `0' AMSK<9:0>: Mask for Address bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 229 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 230 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 17. "UART" (DS70188), which is available on the Microchip web site (www.microchip.com). * Hardware Flow Control Option with UxCTS and UxRTS Pins * Fully Integrated Baud Rate Generator with 16-Bit Prescaler * Baud Rates Ranging from 1 Mbps to 15 bps at 16x mode at 40 MIPS * Baud Rates Ranging from 4 Mbps to 61 bps at 4x mode at 40 MIPS * 4-Deep First-In First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * A Separate Interrupt for all UART Error Conditions * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Support for Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA(R) Support A simplified block diagram of the UART module is shown in Figure 18-1. The UART module consists of these key hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver Note: The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 device families. The UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA(R) encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8-Bit or 9-Bit Data Transmission through the UxTX and UxRX pins * Even, Odd or No Parity Options (for 8-bit data) * One or Two Stop bits FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) Hardware Flow Control UxRTS UxCTS UART Receiver UxRX UART Transmitter UxTX (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 231 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: R/W-0 UARTEN(1) bit 15 R/W-0 HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0, HC ABAUD R/W-0 URXINV R/W-0 BRGH R/W-0 R/W-0 UxMODE: UARTx MODE REGISTER U-0 -- R/W-0 USIDL R/W-0 IREN(2) R/W-0 RTSMD U-0 -- R/W-0 R/W-0 bit 8 R/W-0 STSEL bit 0 UEN<1:0> PDSEL<1:0> UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA(R) Encoder and Decoder Enable bit(2) 1 = IrDA(R) encoder and decoder enabled 0 = IrDA(R) encoder and decoder disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode Unimplemented: Read as `0' UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by port latches WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement disabled or completed URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F Family Reference Manual" for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). DS70318D-page 232 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: bit 3 UxMODE: UARTx MODE REGISTER (CONTINUED) BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit bit 2-1 bit 0 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F Family Reference Manual" for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 233 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: R/W-0 UTXISEL1 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15,13 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set C = Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 ADDEN R-1 RIDLE R-0 PERR R-0 FERR R/C-0 OERR UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 UTXISEL0 U-0 -- R/W-0, HC UTXBRK R/W-0 UTXEN (1) R-0 UTXBF R-1 TRMT bit 8 R-0 URXDA bit 0 UTXINV URXISEL<1:0> UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift register, and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift register (this implies there is at least one character open in the transmit buffer) UTXINV: Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is `0' 0 = UxTX Idle state is `1' If IREN = 1: 1 = IrDA(R) encoded UxTX Idle state is `1' 0 = IrDA(R) encoded UxTX Idle state is `0' bit 14 bit 12 bit 11 Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit(1) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset; UxTX pin controlled by port UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full; at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift register is not empty, a transmission is in progress or queued URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters bit 10 bit 9 bit 8 bit 7-6 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F Family Reference Manual" for information on enabling the UART module for transmit operation. DS70318D-page 234 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: bit 5 UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the UxRSR to the empty state. URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F Family Reference Manual" for information on enabling the UART module for transmit operation. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 235 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 236 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.0 HIGH-SPEED 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 44. "High-Speed 10-Bit Analog-to-Digital Converter (ADC)" (DS70321), which is available on the Microchip web site (www.microchip.com). 19.2 Module Description Note: This ADC module is designed for applications that require low latency between the request for conversion and the resultant output data. Typical applications include: * AC/DC power supplies * DC/DC converters * Power Factor Correction (PFC) This ADC works with the high-speed PWM module in power control applications that require high-frequency control loops. This module can sample and convert two analog inputs in a 0.5 microsecond when two SARs are used. This small conversion delay reduces the "phase lag" between measurement and control system response. Up to five inputs may be sampled at a time (four inputs from the dedicated sample and hold circuits and one from the shared sample and hold circuit). If multiple inputs request conversion, the ADC will convert them in a sequential manner, starting with the lowest order input. This ADC design provides each pair of analog inputs (AN1,AN0), (AN3,AN2),..., the ability to specify its own trigger source out of a maximum of sixteen different trigger sources. This capability allows this ADC to sample and convert analog inputs that are associated with PWM generators operating on independent time bases. The user application typically requires synchronization between analog data sampling and PWM output to the application circuit. The very high-speed operation of this ADC module allows "data on demand". In addition, several hardware features have been added to the peripheral interface to improve real-time performance in a typical DSP based application. Result alignment options Automated sampling External conversion start control Two internal inputs to monitor 1.2V internal reference and EXTREF input signal A block diagram of the ADC module is shown in Figure 19-6. * * * * The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices provide high-speed successive approximation analog to digital conversions to support applications such as AC/DC and DC/DC power converters. 19.1 Features Overview The ADC module comprises the following features: * 10-bit resolution * Unipolar inputs * Up to two Successive Approximation Registers (SARs) * Up to 12 external input channels * Up to two internal analog inputs * Dedicated result register for each analog input * 1 LSB accuracy at 3.3V * Single supply operation * 4 Msps conversion rate at 3.3V (devices with two SARs) * 2 Msps conversion rate at 3.3V (devices with one SAR) * Low-power CMOS technology (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 237 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.3 Module Functionality The high-speed 10-bit ADC module is designed to support power conversion applications when used with the High-Speed PWM module. The ADC may have one or two SAR modules, depending on the device variant. If two SARs are present on a device, two conversions can be processed at a time, yielding 4 Msps conversion rate. If only one SAR is present on a device, only one conversion can be processed at a time, yielding 2 Msps conversion rate. The high-speed 10-bit ADC produces two 10-bit conversion results in a 0.5 microsecond. The ADC module supports up to 12 external analog inputs and two internal analog inputs. To monitor reference voltage, two internal inputs, AN12 and AN13, are connected to the EXTREF and internal band gap voltages (1.2V), respectively. The analog reference voltage is defined as the device supply voltage (AVDD/AVSS). The ADC module uses the following control and status registers: * * * * * * * * ADCON: A/D Control Register ADSTAT: A/D Status Register ADBASE: A/D Base Register(1,2) ADPCFG: A/D Port Configuration Register ADCPC0: A/D Convert Pair Control Register 0 ADCPC1: A/D Convert Pair Control Register 1 ADCPC2: A/D Convert Pair Control Register 2(1) ADCPC3: A/D Convert Pair Control Register 3(1) The ADCON register controls the operation of the ADC module. The ADSTAT register displays the status of the conversion processes. The ADPCFG registers configure the port pins as analog inputs or as digital I/O. The ADCPCx registers control the triggering of the ADC conversions. See Register 19-1 through Register 19-8 for detailed bit configurations. Note: A unique feature of the ADC module is its ability to sample inputs in an asynchronous manner. Individual sample and hold circuits can be triggered independently of each other. DS70318D-page 238 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-1: ADC BLOCK DIAGRAM FOR DSPIC33FJ06GS101 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 Bus Interface SAR Core Eight 16-Bit Registers AN1 AN3 Shared Sample and Hold AN6 AN7 (c) 2009 Microchip Technology Inc. Preliminary Data Format DS70318D-page 239 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 SAR Core Eight 16-Bit Registers AN1 AN3 Shared Sample and Hold AN4 AN5 DS70318D-page 240 Preliminary (c) 2009 Microchip Technology Inc. Bus Interface Data Format DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 SAR Core AN12(1) (EXTREF) Eight 16-Bit Registers AN1 AN3 Shared Sample and Hold AN4 AN5 AN13(2) (INTREF) Note 1: 2: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN13 (INTREF) is an internal analog input and is not available on a pin. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 241 Bus Interface Data Format DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS402/404 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 AN4 Bus Interface SAR Core Ten 16-Bit Registers AN1 AN3 AN5 AN6 Shared Sample and Hold AN7 DS70318D-page 242 Preliminary Data Format (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS502 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 SAR Core AN4 Five 16-Bit Registers AN6 Even numbered inputs with shared S&H Bus Interface AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H AN3 AN5 AN7 SAR Core Five 16-Bit Registers Data Format AN13(2) (INTREF) Note 1: 2: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN13 (INTREF) is an internal analog input and is not available on a pin. (c) 2009 Microchip Technology Inc. Preliminary Data Format DS70318D-page 243 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-6: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS504 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 SAR Core AN4 Seven 16-Bit Registers AN6 AN10 AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H SAR Core Seven 16-Bit Registers Data Format AN3 AN5 AN7 AN9 AN11 AN13(2) (INTREF) AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN13 (INTREF) is an internal analog input and is not available on a pin. Note 1: 2: DS70318D-page 244 Preliminary (c) 2009 Microchip Technology Inc. Bus Interface AN8 Even Numbered Inputs with Shared S&H Data Format DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: R/W-0 ADON bit 15 R/W-0 EIE(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ORDER(1) R/W-0 R/W-0 U-0 -- R/W-0 R/W-1 ADCS<2:0>(1) bit 0 ADCON: A/D CONTROL REGISTER U-0 -- R/W-0 ADSIDL R/W-0 SLOWCLK(1) U-0 -- R/W-0 GSWTRG U-0 -- R/W-0 FORM(1) bit 8 R/W-1 SEQSAMP(1) ASYNCSAMP(1) ADON: A/D Operating Mode bit 1 = A/D converter module is operating 0 = A/D converter is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode SLOWCLK: Enable The Slow Clock Divider bit(1) 1 = ADC is clocked by the auxiliary PLL (ACLK) 0 = ADC is clock by the primary PLL (FVCO) Unimplemented: Read as `0' GSWTRG: Global Software Trigger bit When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). Unimplemented: Read as `0' FORM: Data Output Format bit(1) 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT = 0000 00dd dddd dddd) EIE: Early Interrupt Enable bit(1) 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed ORDER: Conversion Order bit(1) 1 = Odd numbered analog input is converted first, followed by conversion of even numbered input 0 = Even numbered analog input is converted first, followed by conversion of odd numbered input SEQSAMP: Sequential Sample Enable bit(1) 1 = Shared Sample and Hold (S&H) circuit is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion. 0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not currently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 Note 1: This control bit can only be changed while ADC is disabled (ADON = 0), and only applies to single SAR devices. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 245 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: bit 4 ADCON: A/D CONTROL REGISTER (CONTINUED) ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1) 1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger pulse is detected. 0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling process in two ADC clock cycles. Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 bit 3 bit 2-0 Note 1: This control bit can only be changed while ADC is disabled (ADON = 0), and only applies to single SAR devices. DS70318D-page 246 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR C = Clearable bit bit 15-7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0, HS P6RDY(1) R/C-0, HS P5RDY(2) R/C-0, HS P4RDY(2) R/C-0, HS P3RDY(3) R/C-0, HS P2RDY(4) R/C-0, HS P1RDY ADSTAT: A/D STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/C-0, HS P0RDY bit 0 Unimplemented: Read as `0' P6RDY: Conversion Data for Pair 6 Ready bit(1) Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P5RDY: Conversion Data for Pair 5 Ready bit(2) Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P4RDY: Conversion Data for Pair 4 Ready bit(2) Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P3RDY: Conversion Data for Pair 3 Ready bit(3) Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P2RDY: Conversion Data for Pair 2 Ready bit(4) Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P1RDY: Conversion Data for Pair 1 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P0RDY: Conversion Data for Pair 0 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. Note 1: This bit is available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504 and dsPIC33FJ06GS202 devices only. 2: This bit is available in the dsPIC33FJ16GS504 devices only. 3: This bit is available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS502, dsPIC33FJ16GS504 and DSPIC33FJ06GS101 devices only. 4: This bit is available in the dsPIC33FJ16GS504 and dsPIC33FJ16GS502 devices only. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 247 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-3: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 ADBASE<7:1> R/W-0 R/W-0 R/W-0 U-0 -- bit 0 ADBASE: A/D BASE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 ADBASE<15:8> ADBASE<15:1>: This register contains the base address of the user's ADC Interrupt Service Routine jump table. This register, when read, contains the sum of the ADBASE register contents and the encoded value of the PxRDY status bits. The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the highest priority, and P6RDY is the lowest priority. Unimplemented: Read as `0' bit 0 Note 1: The encoding results are shifted left two bits so bits 1-0 of the result are always zero. 2: As an alternative to using the ADBASE Register, the ADCP0-6 ADC Pair Conversion Complete Interrupts can be used to invoke A to D conversion completion routines for individual ADC input pairs. REGISTER 19-4: U-0 -- bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-0 ADPCFG: A/D PORT CONFIGURATION REGISTER U-0 -- U-0 -- U-0 -- R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 PCFG6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PCFG<11:0>: A/D Port Configuration Control bits(1,2,3,4) 1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage Not all PCFGx bits are available on all devices. See Figure 19-1 through Figure 19-6 for the available analog pins (PCFGx = ANx, where x = 0-11). Note: DS70318D-page 248 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: R/W-0 IRQEN1 bit 15 R/W-0 IRQEN0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PEND0 R/W-0 SWTRG0 R/W-0 R/W-0 R/W-0 TRGSRC0<4:0> bit 0 R/W-0 ADCPC0: A/D CONVERT PAIR CONTROL REGISTER 0 R/W-0 R/W-0 SWTRG1 R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> bit 8 R/W-0 R/W-0 R/W-0 PEND1 IRQEN1: Interrupt Request Enable 1 bit 1 = Enable IRQ generation when requested conversion of channels AN3 and AN2 is completed 0 = IRQ is not generated PEND1: Pending Conversion Status 1 bit 1 = Conversion of channels AN3 and AN2 is pending. Set when selected trigger is asserted 0 = Conversion is complete SWTRG1: Software Trigger 1 bit 1 = Start conversion of AN3 and AN2 (if selected in TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND1 bit is set. 0 = Conversion is not started TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of analog channels AN3 and AN2. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * bit 14 bit 13 bit 12-8 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match Note 1: If other conversions are in progress, then conversion will be performed when the conversion resources are available. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 249 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: bit 7 ADCPC0: A/D CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) IRQEN0: Interrupt Request Enable 0 bit 1 = Enable IRQ generation when requested conversion of channels AN1 and AN0 is completed 0 = IRQ is not generated PEND0: Pending Conversion Status 0 bit 1 = Conversion of channels AN1 and AN0 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG0: Software Trigger 0 bit 1 = Start conversion of AN1 and AN0 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND0 bit is set. 0 = Conversion is not started TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of analog channels AN1 and AN0. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * bit 6 bit 5 bit 4-0 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match Note 1: If other conversions are in progress, then conversion will be performed when the conversion resources are available. DS70318D-page 250 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: R/W-0 IRQEN3 bit 15 R/W-0 IRQEN2(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PEND2(2) R/W-0 SWTRG2(2) R/W-0 R/W-0 R/W-0 TRGSRC2<4:0>(2) bit 0 R/W-0 (1) ADCPC1: A/D CONVERT PAIR CONTROL REGISTER 1 R/W-0 R/W-0 SWTRG3(1) R/W-0 R/W-0 R/W-0 TRGSRC3<4:0>(1) bit 8 R/W-0 R/W-0 R/W-0 PEND3(1) IRQEN3: Interrupt Request Enable 3 bit(1) 1 = Enable IRQ generation when requested conversion of channels AN7 and AN6 is completed 0 = IRQ is not generated PEND3: Pending Conversion Status 3 bit(1) 1 = Conversion of channels AN7 and AN6 is pending. Set when selected trigger is asserted 0 = Conversion is complete SWTRG3: Software Trigger 3 bit(1) 1 = Start conversion of AN7 and AN6 (if selected in TRGSRC bits)(3) This bit is automatically cleared by hardware when the PEND3 bit is set. 0 = Conversion is not started bit 14 bit 13 Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and DSPIC33FJ06GS101 devices only. 2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102, dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only. 3: If other conversions are in progress, then conversion will be performed when the conversion resources are available. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 251 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: bit 12-8 ADCPC1: A/D CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of analog channels AN7 and AN6. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match bit 7 IRQEN2: Interrupt Request Enable 2 bit(2) 1 = Enable IRQ generation when requested conversion of channels AN5 and AN4 is completed 0 = IRQ is not generated PEND2: Pending Conversion Status 2 bit(2) 1 = Conversion of channels AN5 and AN4 is pending; set when selected trigger is asserted. 0 = Conversion is complete SWTRG2: Software Trigger 2 bit(2) 1 = Start conversion of AN5 and AN4 (if selected by TRGSRC bits)(3) This bit is automatically cleared by hardware when the PEND2 bit is set. 0 = Conversion is not started bit 6 bit 5 Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and DSPIC33FJ06GS101 devices only. 2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102, dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only. 3: If other conversions are in progress, then conversion will be performed when the conversion resources are available. DS70318D-page 252 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: bit 4-0 ADCPC1: A/D CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) TRGSRC2<4:0>: Trigger 2 Source Selection bits Selects trigger source for conversion of analog channels AN5 and AN4. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and DSPIC33FJ06GS101 devices only. 2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102, dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only. 3: If other conversions are in progress, then conversion will be performed when the conversion resources are available. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 253 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: R/W-0 IRQEN5 bit 15 R/W-0 IRQEN4 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PEND4 R/W-0 SWTRG4 R/W-0 R/W-0 R/W-0 TRGSRC4<4:0> bit 0 R/W-0 ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2(1) R/W-0 R/W-0 SWTRG5 R/W-0 R/W-0 R/W-0 TRGSRC5<4:0> bit 8 R/W-0 R/W-0 R/W-0 PEND5 IRQEN5: Interrupt Request Enable 5 bit 1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed 0 = IRQ is not generated PEND5: Pending Conversion Status 5 bit 1 = Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG5: Software Trigger 5 bit 1 = Start conversion of AN11 and AN10 (if selected in TRGSRC bits)(2) This bit is automatically cleared by hardware when the PEND5 bit is set. 0 = Conversion is not started bit 14 bit 13 Note 1: This register is only implemented on the dsPIC33FJ16GS504 devices. 2: If other conversions are in progress, then conversion will be performed when the conversion resources are available. DS70318D-page 254 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: bit 12-8 ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2(1) (CONTINUED) TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of analog channels AN11 and AN10. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match bit 7 IRQEN4: Interrupt Request Enable 4 bit 1 = Enable IRQ generation when requested conversion of channels AN9 and AN8 is completed 0 = IRQ is not generated PEND4: Pending Conversion Status 4 bit 1 = Conversion of channels AN9 and AN8 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG4: Software Trigger4 bit 1 = Start conversion of AN9 and AN8 (if selected by TRGSRC bits)(2) This bit is automatically cleared by hardware when the PEND4 bit is set. 0 = Conversion is not started bit 6 bit 5 Note 1: This register is only implemented on the dsPIC33FJ16GS504 devices. 2: If other conversions are in progress, then conversion will be performed when the conversion resources are available. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 255 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: bit 4-0 ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2(1) (CONTINUED) TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of analog channels AN9 and AN8. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match Note 1: This register is only implemented on the dsPIC33FJ16GS504 devices. 2: If other conversions are in progress, then conversion will be performed when the conversion resources are available. DS70318D-page 256 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: U-0 -- bit 15 R/W-0 IRQEN6 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PEND6 R/W-0 SWTRG6 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> bit 0 R/W-0 ADCPC3: A/D CONVERT PAIR CONTROL REGISTER 3(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' IRQEN6: Interrupt Request Enable 6 bit 1 = Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed 0 = IRQ is not generated PEND6: Pending Conversion Status 6 bit 1 = Conversion of channels AN13 and AN 12 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG6: Software Trigger 6 bit 1 = Start conversion of AN13 (INTREF) and AN12 (EXTREF) (if selected by TRGSRC bits)(2) This bit is automatically cleared by hardware when the PEND6 bit is set. 0 = Conversion is not started bit 6 bit 5 Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices. 2: If other conversions are in progress, conversion will be performed when the conversion resources are available. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 257 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: bit 4-0 ADCPC3: A/D CONVERT PAIR CONTROL REGISTER 3(1) (CONTINUED) TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of analog channels AN13 and AN12. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = Reserved * * * 01100 = Timer1 period match 01101 = Reserved 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = Reserved * * * 10110 = Reserved 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = Reserved * * * 11111 = Timer2 period match Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices. 2: If other conversions are in progress, conversion will be performed when the conversion resources are available. DS70318D-page 258 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.0 Note: HIGH-SPEED ANALOG COMPARATOR This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual", Section 45. "High-Speed Analog Comparator" (DS70296), which is available on the Microchip web site (www.microchip.com). * DAC has three ranges of operation: - AVDD/2 - Internal Reference 1.2V, 1% - External Reference < (AVDD - 1.6V) * ADC sample and convert trigger capability * Disable capability reduces power consumption * Functional support for PWM module: - PWM duty cycle control - PWM period control - PWM Fault detect 20.2 Module Description The dsPIC33F SMPS Comparator module monitors current and/or voltage transients that may be too fast for the CPU and ADC to capture. 20.1 Features Overview The SMPS comparator module offers the following major features: * * * * * * 16 selectable comparator inputs Up to four analog comparators 10-bit DAC for each analog comparator Programmable output polarity Interrupt generation capability DACOUT pin to provide DAC output Figure 20-1 shows a functional block diagram of one analog comparator from the SMPS comparator module. The analog comparator provides high-speed operation with a typical delay of 20 ns. The comparator has a typical offset voltage of 5 mV. The negative input of the comparator is always connected to the DAC circuit. The positive input of the comparator is connected to an analog multiplexer that selects the desired source pin. The analog comparator input pins are typically shared with pins used by the Analog-to-Digital Converter (ADC) module. Both the comparator and the ADC can use the same pins at the same time. This capability enables a user to measure an input voltage with the ADC and detect voltage transients with the comparator. FIGURE 20-1: CMPxA(1) CMPxB(1) CMPxC(1) CMPxD(1) COMPARATOR MODULE BLOCK DIAGRAM INSEL<1:0> ACMPx (Trigger to PWM)(1) Status M U X CMPx* 0 Glitch Filter 1 Pulse Generator RANGE AVDD/2 INTREF M U X CMPPOL DAC AVSS 10 DACOE DACOUT Interrupt Request CMREF EXTREF Note 1: x = 1, 2, 3, and 4. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 259 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.3 Module Applications 20.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks. The comparator module has a high-speed comparator and an associated 10-bit DAC that provides a programmable reference voltage to the inverting input of the comparator. The polarity of the comparator output is user-programmable. The output of the module can be used in the following modes: * * * * * Generate an Interrupt Trigger an ADC Sample and Convert Process Truncate the PWM Signal (current limit) Truncate the PWM Period (current minimum) Disable the PWM Outputs (Fault latch) If the comparator module is enabled and a pin has been selected as the source for the comparator, then the chosen I/O pad must disable the digital input buffer associated with the pad to prevent excessive currents in the digital buffer due to analog input voltages. 20.6 Digital Logic The CMPCONx register (see Register 20-1) provides the control logic that configures the comparator module. The digital logic provides a glitch filter for the comparator output to mask transient signals in less than two instruction cycles. In Sleep or Idle mode, the glitch filter is bypassed to enable an asynchronous path from the comparator to the interrupt controller. This asynchronous path can be used to wake-up the processor from Sleep or Idle mode. The comparator can be disabled while in Idle mode if the CMPSIDL bit is set. If a device has multiple comparators, if any CMPSIDL bit is set, then the entire group of comparators will be disabled while in Idle mode. This behavior reduces complexity in the design of the clock control logic for this module. The digital logic also provides a one TCY width pulse generator for triggering the ADC and generating interrupt requests. The CMPDACx (see Register 20-2) register provides the digital input value to the reference DAC. If the module is disabled, the DAC and comparator are disabled to reduce power consumption. The output of the comparator module may be used in multiple modes at the same time, such as: (1) generate an interrupt, (2) have the ADC take a sample and convert it, and (3) truncate the PWM output in response to a voltage being detected beyond its expected value. The comparator module can also be used to wake-up the system from Sleep or Idle mode when the analog input voltage exceeds the programmed threshold voltage. 20.4 DAC The range of the DAC is controlled via an analog multiplexer that selects either AVDD/2, internal 1.2V, 1% reference, or an external reference source, EXTREF. The full range of the DAC (AVDD/2) will typically be used when the chosen input source pin is shared with the ADC. The reduced range option (INTREF) will likely be used when monitoring current levels using a current sense resistor. Usually, the measured voltages in such applications are small (<1.25V); therefore the option of using a reduced reference range for the comparator extends the available DAC resolution in these applications. The use of an external reference enables the user to connect to a reference that better suits their application. DACOUT, shown in Figure 20-1, can only be associated with a single comparator at a given time. Note: It should be ensured in software that multiple DACOE bits are not set. The output on the DACOUT pin will be indeterminate if multiple comparators enable the DAC output. 20.7 Comparator Input Range The comparator has a limitation for the input Common Mode Range (CMR) of (AVDD - 1.5V), typical. This means that both inputs should not exceed this range. As long as one of the inputs is within the Common Mode Range, the comparator output will be correct. However, any input exceeding the CMR limitation will cause the comparator input to be saturated. If both inputs exceed the CMR, the comparator output will be indeterminate. 20.8 DAC Output Range The DAC has a limitation for the maximum reference voltage input of (AVDD - 1.6) volts. An external reference voltage input should not exceed this value or the reference DAC output will become indeterminate. 20.9 Comparator Registers The comparator module is controlled by the following registers: * CMPCONx: Comparator Control Register * CMPDACx: Comparator DAC Control Register DS70318D-page 260 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 20-1: R/W-0 CMPON bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 EXTREF U-0 -- R/W-0 CMPSTAT U-0 -- R/W-0 CMPPOL CMPCONx: COMPARATOR CONTROL REGISTER U-0 -- R/W-0 CMPSIDL U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DACOE bit 8 R/W-0 RANGE bit 0 INSEL<1:0> CMPON: Comparator Operating Mode bit 1 = Comparator module is enabled 0 = Comparator module is disabled (reduces power consumption) Unimplemented: Read as `0' CMPSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode. 0 = Continue module operation in Idle mode If a device has multiple comparators, any CMPSIDL bit set to `1' disables ALL comparators while in Idle mode. Reserved: Read as `0' DACOE: DAC Output Enable 1 = DAC analog voltage is output to DACOUT pin(1) 0 = DAC analog voltage is not connected to DACOUT pin INSEL<1:0>: Input Source Select for Comparator bits 00 = Select CMPxA input pin 01 = Select CMPxB input pin 10 = Select CMPxC input pin 11 = Select CMPxD input pin EXTREF: Enable External Reference bit 1 = External source provides reference to DAC (maximum DAC voltage determined by external voltage source) 0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by RANGE bit setting) Reserved: Read as `0' CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit Reserved: Read as `0' CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non-inverted RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD 0 = Low Range: Max DAC Value = INTREF, 1.2V, 1% bit 14 bit 13 bit 12-9 bit 8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DACOUT can be associated only with a single comparator at any given time. The software must ensure that multiple comparators do not enable the DAC output by setting their respective DACOE bit. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 261 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 20-2: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMPDACx: COMPARATOR DAC CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 R/W-0 bit 0 CMREF<9:8> CMREF<7:0> Reserved: Read as `0' CMREF<9:0>: Comparator Reference Voltage Select bits 1111111111 = (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on RANGE bit or (CMREF * EXTREF/1024) if EXTREF is set * * * 0000000000 = 0.0 volts DS70318D-page 262 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F Family Reference Manual" sections. 21.1 Configuration Bits The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. The individual Configuration bit descriptions for the FBS, FGS, FOSCSEL, FOSC, FWDT, FPOR and FICD Configuration registers are shown in Table 21-2. Note that address, 0xF80000, is beyond the user program memory space. It belongs to the configuration memory space (0x800000-0xFFFFFF), which can only be accessed using table reads and table writes. The upper byte of all device Configuration registers should always be `1111 1111'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation. To prevent inadvertent configuration changes during code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires that power to the device be cycled. The device Configuration register map is shown in Table 21-1. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection and CodeGuardTM Security JTAG Boundary Scan Interface In-Circuit Serial ProgrammingTM (ICSPTM) In-Circuit Emulation Brown-out Reset (BOR) TABLE 21-1: Address 0xF80000 FBS DEVICE CONFIGURATION REGISTER MAP Name Bit 7 -- -- IESO FWDTEN -- Bit 6 -- -- -- WINDIS -- Bit 5 -- -- -- IOL1WAY -- -- JTAGEN -- WDTPRE -- -- -- -- -- Bit 4 -- Reserved(1) -- -- -- -- GSS<1:0> FNOSC<2:0> OSCIOFNC POSCMD<1:0> WDTPOST<3:0> FPWRT<2:0> ICS<1:0> GWRP Bit 3 Bit 2 BSS<2:0> Bit 1 Bit 0 BWRP 0xF80002 RESERVED 0xF80004 FGS 0xF80006 FOSCSEL 0xF80008 FOSC 0xF8000A FWDT 0xF8000C FPOR 0xF8000E FICD 0xF80010 FUID0 0xF80012 FUID1 Note 1: FCKSM<1:0> Reserved(1) User Unit ID Byte 0 User Unit ID Byte 1 When read, these bits will appear as `1'. When you write to these bits, set these bits to `1'. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 263 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: Bit Field BWRP dsPIC33F CONFIGURATION BITS DESCRIPTION Register FBS Description Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected Boot Segment Program Flash Code Protection Size bits X11 = No boot program Flash segment Boot space is 256 instruction words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0003FE 010 = High security; boot program Flash segment ends at 0x0003FE Boot space is 768 instruction words (except interrupt vectors) 101 = Standard security; boot program Flash segment ends at 0x0007FE 001 = High security; boot program Flash segment ends at 0x0007FE Boot space is 1792 instruction words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x000FFE 000 = High security; boot program Flash segment ends at 0x000FFE BSS<2:0> FBS GSS<1:0> FGS General Segment Code-Protect bits 11 = User program memory is not code-protected 10 = Standard security 0x = High security General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode GWRP FGS IESO FOSCSEL FNOSC<2:0> FOSCSEL FCKSM<1:0> FOSC IOL1WAY FOSC OSCIOFNC FOSC POSCMD<1:0> FOSC DS70318D-page 264 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: Bit Field FWDTEN dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FWDT Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 * * * 0001 = 1:2 0000 = 1:1 Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICD Communication Channel Select Enable bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use. WINDIS FWDT WDTPRE FWDT WDTPOST<3:0> FWDT FPWRT<2:0> FPOR JTAGEN FICD ICS<1:0> FICD (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 265 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.2 On-Chip Voltage Regulator 21.3 BOR: Brown-Out Reset The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the VCAP/VDDCORE pin (Figure 21-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 24-13 located in Section 24.1 "DC Characteristics". Note: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/VDDCORE pin. The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage VCAP/VDDCORE. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC<2:0> and POSCMD<1:0>). If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON<5>) is `1'. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case is TFSCM. The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. On a POR, it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. FIGURE 21-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2) 3.3V dsPIC33F VDD VCAP/VDDCORE CEFC VSS Note 1: 2: These are typical operating voltages. Refer to Table 24-13 located in Section 24.1 "DC Characteristics" for the full operating ranges of VDD and VCAP/VDDCORE. It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/VDDCORE pin. DS70318D-page 266 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.4 Watchdog Timer (WDT) 21.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. For DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 21.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST<3:0> Configuration bits (FWDT<3:0>) which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 21.4.3 ENABLING WDT The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. Note: If the WINDIS bit (FWDT<6>) is cleared, the CLRWDT instruction should be executed by the application software only during the last 1/4 of the WDT period. This CLRWDT window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. The WDT flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. FIGURE 21-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle SWDTEN FWDTEN WDTPRE WDTPOST<3:0> WDT Wake-up 1 WDT Reset LPRC Clock RS Prescaler (Divide by N1) RS Postscaler (Divide by N2) 0 WINDIS WDT Window Select CLRWDT Instruction (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 267 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.5 JTAG Interface 21.7 In-Circuit Debugger DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of the document. When MPLAB(R) ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: * PGEC1 and PGED1 * PGEC2 and PGED2 * PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 21.6 In-Circuit Serial Programming DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family digital signal controllers can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) for details about In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: * PGEC1 and PGED1 * PGEC2 and PGED2 * PGEC3 and PGED3 DS70318D-page 268 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.8 Code Protection and CodeGuardTM Security The code protection features are controlled by the Configuration registers: FBS and FGS. Secure segment and RAM protection is not implemented in DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. Note: Refer to CodeGuard Security Reference Manual (DS70180) for further information on usage, configuration and operation of CodeGuard Security. The DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices offer the intermediate implementation of CodeGuardTM Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. When coupled with software encryption libraries, CodeGuardTM Security can be used to securely update Flash even when multiple IPs reside on a single chip. TABLE 21-3: CODE FLASH SECURITY SEGMENT SIZES FOR 6-Kbyte DEVICES VS = 256 IW 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh VS = 256 IW BS = 256 IW 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh VS = 256 IW 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh VS = 256 IW 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh TABLE 21-4: CODE FLASH SECURITY SEGMENT SIZES FOR 16-Kbyte DEVICES VS = 256 IW 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh VS = 256 IW BS = 256 IW 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh 000000h 0001FEh 000200h 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h 002BFEh Configuration Bits Configuration Bits BSS<2:0> = x11 0K GS = 1792 IW BSS<2:0> = x11 0K GS = 5376 IW BSS<2:0> = x10 GS = 1536 IW 256 BSS<2:0> = x10 256 GS = 5120 IW VS = 256 IW BSS<2:0> = x01 768 GS = 4608 IW VS = 256 IW BSS<2:0> = x00 1792 GS = 3584 IW BS = 1792 IW BS = 768 IW BSS<2:0> = x01 768 BS = 768 IW GS = 1024 IW BSS<2:0> = x00 1792 BS = 1792 IW (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 269 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 270 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 22.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F Family Reference Manual" sections. Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple * The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb') The literal instructions that involve data movement can use some of the following operands: * A literal value to be loaded into a W register or file register (specified by `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand, which is a register `Wb' without any address modifier * The second source operand, which is a literal value * The destination of the result (only if not the same as the first source operand), which is typically a register `Wd' with or without an address modifier The MAC class of DSP instructions can use some of the following operands: * The accumulator (A or B) to be used (required operand) * The W registers to be used as the two operands * The X and Y address space prefetch operations * The X and Y address space prefetch destinations * The accumulator write-back destination The other DSP instructions do not involve any multiplication and can include: * The accumulator to be used (required) * The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier * The amount of shift specified by a W register, `Wn', or a literal value The control instructions can use some of the following operands: * A program memory address * The mode of the table read and table write instructions The dsPIC33F instruction set is identical to that of the dsPIC30F. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: * * * * * Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations Table 22-1 shows the general symbols used in describing the instructions. The dsPIC33F instruction set summary in Table 22-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand, which is typically a register `Wb' without any address modifier * The second source operand, which is typically a register `Ws' with or without an address modifier * The destination of the result, which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value, `f' * The destination, which could be either the file register, `f', or the W0 register, which is denoted as `WREG' (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 271 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157). TABLE 22-1: Field #text (text) [text] {} SYMBOLS USED IN OPCODE DESCRIPTIONS Description Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) One of two accumulators {A, B} Accumulator Write-Back Destination Address register {W13, [W13]+ = 2} 4-bit bit selection field (used in word-addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0x0000...0x1FFF} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSb must be `0' Field does not require an entry, can be blank DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor Working register pair (Direct Addressing) DS70318D-page 272 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-1: Field Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Description Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} One of 16 Working registers {W0..W15} One of 16 Destination Working registers {W0...W15} One of 16 Source Working registers {W0...W15} W0 (Working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } X Data Space Prefetch Address register for DSP instructions {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} X Data Space Prefetch Destination register for DSP instructions {W4...W7} Y Data Space Prefetch Address register for DSP instructions {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Y Data Space Prefetch Destination register for DSP instructions {W4...W7} Wxd Wy Wyd (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 273 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 1 Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADD ADD 2 ADDC ADDC ADDC ADDC ADDC ADDC 3 AND AND AND AND AND AND 4 ASR ASR ASR ASR ASR ASR 5 6 BCLR BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA 7 8 9 BSET BSET BSET BSW BSW.C BSW.Z BTG BTG BTG INSTRUCTION SET OVERVIEW Assembly Syntax Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Wso,#Slit4,Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OA,Expr OB,Expr OV,Expr SA,Expr SB,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Description Add Accumulators f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 16-Bit Signed Add to Accumulator f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater Than or Equal Branch if Unsigned Greater Than or Equal Branch if Greater Than Branch if Unsigned Greater Than Branch if Less Than or Equal Branch if Unsigned Less Than or Equal Branch if Less Than Branch if Unsigned Less Than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Accumulator A Overflow Branch if Accumulator B Overflow Branch if Overflow Branch if Accumulator A Saturated Branch if Accumulator B Saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws DS70318D-page 274 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 10 Assembly Mnemonic BTSC BTSC BTSC 11 BTSS BTSS BTSS 12 BTST BTST BTST.C BTST.Z BTST.C BTST.Z 13 BTSTS BTSTS BTSTS.C BTSTS.Z 14 15 CALL CALL CALL CLR CLR CLR CLR CLR 16 17 CLRWDT COM CLRWDT COM COM COM 18 CP CP CP CP 19 20 CP0 CP0 CP0 CPB CPB CPB CPB 21 22 23 24 25 26 CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC 27 DEC2 DEC2 DEC2 DEC2 28 DISI DISI f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb, Wn Wb, Wn Wb, Wn Wb, Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Acc,Wx,Wxd,Wy,Wyd,AWB Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 275 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 29 Assembly Mnemonic DIV DIV.S DIV.SD DIV.U DIV.UD 30 31 32 33 34 35 36 37 38 39 DIVF DO DIVF DO DO ED EDAC EXCH FBCL FF1L FF1R GOTO ED EDAC EXCH FBCL FF1L FF1R GOTO GOTO INC INC INC INC 40 INC2 INC2 INC2 INC2 41 IOR IOR IOR IOR IOR IOR 42 43 44 LAC LNK LSR LAC LNK LSR LSR LSR LSR LSR 45 MAC MAC INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wm,Wn #lit14,Expr Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd Wm*Wm,Acc,Wx,Wy,Wxd Wns,Wnd Ws,Wnd Ws,Wnd Ws,Wnd Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Wso,#Slit4,Acc #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd Wm*Wn,Acc,Wx,Wxd,Wy,Wyd , AWB Wm*Wm,Acc,Wx,Wxd,Wy,Wyd f,Wn f f,WREG #lit16,Wn #lit8,Wn Wn,f Wso,Wdo WREG,f Wns,Wd Ws,Wnd Acc,Wx,Wxd,Wy,Wyd,AWB Description Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Signed 16/16-bit Fractional Divide Do code to PC + Expr, lit14 + 1 times Do code to PC + Expr, (Wn) + 1 times Euclidean Distance (no accumulate) Euclidean Distance Swap Wns with Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Load Accumulator Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Multiply and Accumulate # of # of Words Cycles 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 18 18 18 18 2 2 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Flags Affected N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV None None OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None C C C None None C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z N,Z N,Z N,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB None C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None N,Z N,Z None None None None N,Z None None None MAC 46 MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV.D MOV.D 47 MOVSAC MOVSAC Square and Accumulate Move f to Wn Move f to f Move f to WREG Move 16-Bit Literal to Wn Move 8-Bit Literal to Wn Move Wn to f Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns + 1) to Wd Move Double from Ws to W(nd + 1):W(nd) Prefetch and Store Accumulator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 DS70318D-page 276 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 48 Assembly Mnemonic MPY INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Description Multiply Wm by Wn to Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator # of # of Words Cycles 1 1 1 1 1 1 1 1 Status Flags Affected OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None OA,OB,OAB, SA,SB,SAB None None None None None None None OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None All None None None None WDTO,Sleep None None None None None None None None C,N,Z C,N,Z C,N,Z N,Z N,Z N,Z C,N,Z C,N,Z C,N,Z 49 50 MPY.N MSC MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f Acc f f,WREG Ws,Wd 51 MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) W3:W2 = f * WREG Negate Accumulator f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns + 1) to Top-of-Stack (TOS) Push Shadow Registers Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 52 NEG NEG NEG NEG NEG 53 54 NOP NOP NOPR POP POP POP POP.D POP.S f Wdo Wnd 55 PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns 56 57 58 59 60 61 62 63 PWRSAV RCALL PWRSAV RCALL RCALL #lit1 Expr Wn #lit14 Wn REPEAT REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd #lit10,Wn 64 RLNC RLNC RLNC RLNC 65 RRC RRC RRC RRC (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 277 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 66 Assembly Mnemonic RRNC RRNC RRNC RRNC 67 68 69 SAC SAC SAC.R SE SETM SE SETM SETM SETM 70 SFTAC SFTAC SFTAC 71 SL SL SL SL SL SL 72 SUB SUB SUB SUB SUB SUB SUB 73 SUBB SUBB SUBB SUBB SUBB SUBB 74 SUBR SUBR SUBR SUBR SUBR 75 SUBBR SUBBR SUBBR SUBBR SUBBR 76 77 78 79 80 81 82 SWAP SWAP.b SWAP TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR 83 ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f f,WREG Ws,Wd Acc,#Slit4,Wdo Acc,#Slit4,Wdo Ws,Wnd f WREG Ws Acc,Wn Acc,#Slit6 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd Ws,Wd Ws,Wd Ws,Wd Description f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Store Accumulator Store Rounded Accumulator Wnd = Sign-Extended Ws f = 0xFFFF WREG = 0xFFFF Ws = 0xFFFF Arithmetic Shift Accumulator by (Wn) Arithmetic Shift Accumulator by Slit6 f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 Subtract Accumulators f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 Status Flags Affected N,Z N,Z N,Z None None C,N,Z None None None OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None None None N,Z N,Z N,Z N,Z N,Z C,Z,N DS70318D-page 278 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.0 DEVELOPMENT SUPPORT 23.1 MPLAB Integrated Development Environment Software The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 279 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.2 MPASM Assembler 23.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 23.6 23.3 MPLAB C18 and MPLAB C30 C Compilers MPLAB SIM Software Simulator The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 23.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of linking many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS70318D-page 280 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 23.9 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost-effective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 23.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 23.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 281 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 23.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 23.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS70318D-page 282 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V Voltage on VCAP/VDDCORE with respect to VSS ...................................................................................... 2.25V to 2.75V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA Maximum output current sourced by any I/O pin(3) ...................................................................................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(2) ...............................................................................................................200 mA Maximum output current sunk by non-remappable PWM pins ...............................................................................16 mA Maximum output current sourced by non-remappable PWM pins ..........................................................................16 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2). 3: Exceptions are PWMxL, and PWMxH, which are able to sink/source 16 mA, and digital pins, which are able to sink/source 8 mA. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 283 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.1 DC Characteristics OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) 3.0-3.6V 3.0-3.6V Temp Range (in C) -40C to +85C -40C to +125C DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 40 40 TABLE 24-1: TABLE 24-2: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA TJ TA Min -40 -40 -40 -40 Typ -- -- -- -- Max +125 +85 +140 +125 Unit C C C C Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Extended Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: I/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W PD PINT + PI/O W TABLE 24-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol JA JA JA JA JA JA Typ 28 39 42 47 34 57 Max -- -- -- -- -- -- Unit C/W C/W C/W C/W C/W C/W Notes 1 1 1 1 1 1 Package Thermal Resistance, 44-Pin QFN Package Thermal Resistance, 44-Pin TFQP Package Thermal Resistance, 28-Pin SPDIP Package Thermal Resistance, 28-Pin SOIC Package Thermal Resistance, 28-Pin QFN-S Package Thermal Resistance, 18-Pin SOIC Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70318D-page 284 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage Supply Voltage DC10 DC12 DC16 VDD VDR VPOR 3.0 RAM Data Retention Voltage(2) 1.8 -- VDD Start Voltage(4) to Ensure Internal Power-on Reset Signal VDD Rise Rate(3) to Ensure Internal Power-on Reset Signal VDD Core Internal Regulator Voltage -- -- -- 3.6 -- VSS V V V Industrial and extended DC17 SVDD 0.03 -- -- V/ms 0-3.0V in 0.1s DC18 VCORE 2.25 -- 2.75 V Voltage is dependent on load, temperature and VDD Note 1: 2: 3: 4: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. This is the limit to which VDD may be lowered without losing RAM data. These parameters are characterized but not tested in manufacturing. VDD voltage must remain at VSS for a minimum of 200 s to ensure POR. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 285 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max Units Conditions DC CHARACTERISTICS Parameter Typical(1) No. Operating Current (IDD)(2) DC20d 55 70 mA -40C DC20a 55 70 mA +25C 10 MIPS 3.3V See Note 2 DC20b 55 70 mA +85C DC20c 55 70 mA +125C DC21d 68 85 mA -40C DC21a 68 85 mA +25C 16 MIPS 3.3V See Note 2 and Note 3 DC21b 68 85 mA +85C DC21c 68 85 mA +125C DC22d 78 95 mA -40C DC22a 78 95 mA +25C 20 MIPS 3.3V See Note 2 and Note 3 DC22b 78 95 mA +85C DC22c 78 95 mA +125C DC23d 88 110 mA -40C DC23a 88 110 mA +25C 30 MIPS 3.3V See Note 2 and Note 3 DC23b 88 110 mA +85C DC23c 88 110 mA +125C DC24d 98 120 mA -40C DC24a 98 120 mA +25C 40 MIPS 3.3V See Note 2 DC24b 98 120 mA +85C DC24c 98 120 mA +125C DC25d 128 160 mA -40C 40 MIPS DC25a 125 150 mA +25C See Note 2, except PWM is 3.3V operating at maximum speed DC25b 121 150 mA +85C (PTCON2 = 0x0000) DC25c 119 150 mA +125C DC26d 115 140 mA -40C 40 MIPS DC26a 112 140 mA +25C See Note 2, except PWM is 3.3V operating at 1/2 speed DC26b 110 140 mA +85C (PTCON2 = 0x0001) DC26c 108 140 mA +125C DC27d 111 140 mA -40C 40 MIPS DC27a 108 130 mA +25C See Note 2, except PWM is 3.3V operating at 1/4 speed DC27b 105 130 mA +85C (PTCON2 = 0x0002) DC27c 103 130 mA +125C DC28d 102 130 mA -40C 40 MIPS DC28a 100 120 mA +25C See Note 2, except PWM is 3.3V operating at 1/8 speed DC28b 100 120 mA +85C (PTCON2 = 0x0003) DC28c 100 120 mA +125C Note 1: Data in "Typical" column is at 3.3V, +25C unless otherwise stated. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating (PMD bits are all set). 3: These parameters are characterized but not tested in manufacturing. DS70318D-page 286 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC40d DC40a DC40b DC40c DC41d DC41a DC41b DC41c DC42d DC42a DC42b DC42c DC43d DC43a DC43b DC43c DC44d DC44a DC44b DC44c Note 1: 2: 3: Typical(1) Idle Current (IIDLE): Core Off Clock On Base Current(2) 80 80 80 80 81 81 81 81 82 82 82 82 84 84 84 84 86 86 86 86 100 100 100 100 100 100 100 100 100 100 100 100 105 105 105 105 105 105 105 105 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C +125C 3.3V 40 MIPS 3.3V 30 MIPS(3) 3.3V 20 MIPS(3) 3.3V 16 MIPS(3) 3.3V 10 MIPS Data in "Typical" column is at 3.3V, +25C unless otherwise stated. Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS. These parameters are characterized but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 287 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC60d DC60a DC60b DC60c DC61d DC61a DC61b DC61c Note 1: 2: 3: 4: Typical(1) Power-Down Current (IPD)(2,4) 304 317 321 800 40 40 40 80 500 500 500 950 50 50 50 90 A A A A A A A A -40C +25C +85C +125C -40C +25C +85C +125C 3.3V Watchdog Timer Current: IWDT(3) 3.3V Base Power-Down Current Data in the Typical column is at 3.3V, +25C unless otherwise stated. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1. The current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max 105 105 105 105 105 105 105 105 105 105 105 105 Doze Ratio 1:2 1:64 1:128 1:2 1:64 1:128 1:2 1:64 1:128 1:2 1:64 1:128 Units mA mA mA mA mA mA mA mA mA mA mA mA +125C 3.3V 40 MIPS +85C 3.3V 40 MIPS +25C 3.3V 40 MIPS -40C 3.3V 40 MIPS Conditions DC CHARACTERISTICS Parameter No. DC73a DC73f DC73g DC70a DC70f DC70g DC71a DC71f DC71g DC72a DC72f DC72g Note 1: Typical(1) 86 86 86 86 86 86 86 86 86 86 86 86 Data in the Typical column is at 3.3V, +25C unless otherwise stated. DS70318D-page 288 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Input Low Voltage I/O Pins MCLR I/O Pins with OSC1 I/O Pins with SDAx, SCLx I/O Pins with SDAx, SCLx VIH DI20 DI21 ICNPU DI30 IIL DI50 Input Leakage Current(2,3,4) I/O Pins with: 4 mA Source/Sink Capability 8 mA Source/Sink Capability 16 mA Source/Sink Capability DI55 DI56 ISINK MCLR OSC1 Sink Current Pins: RA3, RA4, RB3, RB4, RB11-RB14 Pins: RC3-RC8, RC11-RC13 Pins: RA0-RA2, RB0, RB1, RB5-RB10, RB15, RC1, RC2, RC9, RC10 -- -- -- -- -- 2 4 8 -- -- -- -- -- 2 2 A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes Input High Voltage I/O Pins Not 5V Tolerant(4) I/O Pins 5V Tolerant(4) CNx Pull-up Current -- 250 -- A VDD = 3.3V, VPIN = VSS 0.7 VDD 0.7 VDD -- -- VDD 5.5 V V VSS VSS VSS VSS VSS -- -- -- -- -- 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD V V V V V SMbus disabled SMbus enabled Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL DI10 DI15 DI16 DI18 DI19 -- -- -- 16 8 4 -- -- -- mA mA mA Note 1: 2: 3: 4: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. See "Pin Diagrams" for the list of 5V tolerant I/O pins. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 289 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Output Low Voltage I/O Ports: 4 mA Source/Sink Capability 8 mA Source/Sink Capability 16 mA Source/Sink Capability DO16 DO20 VOH OSC2/CLKO Output High Voltage I/O Ports: 4 mA Source/Sink Capability 8 mA Source/Sink Capability 16 mA Source/Sink Capability DO26 OSC2/CLKO ISOURCE Source Current Pins: RA3, RA4, RB3, RB4, RB11-RB14 Pins: RC3-RC8, RC11-RC13 Pins: RA0-RA2, RB0, RB1, RB5RB10, RB15, RC1, RC2, RC9, RC10 -- -- -- -- 2.40 2.40 2.40 2.41 -- -- -- -- V V V V IOH = -4 mA, VDD = 3.3V IOH = -8 mA, VDD = 3.3V IOH = -16 mA, VDD = 3.3V IOH = -1.3 mA, VDD = 3.3V -- -- -- -- 0.4 0.4 0.4 0.4 -- -- -- -- V V V V IOL = 4 mA, VDD = 3.3V IOL = 8 mA, VDD = 3.3V IOL = 16 mA, VDD = 3.3V IOL = 2 mA, VDD = 3.3V Min Typ Max Units Conditions Param Symbol No. DO10 VOL -- -- -- 16 8 4 -- -- -- mA mA mA TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic BOR Event on VDD Transition High-to-Low BOR Event is Tied to VDD Core Voltage Decrease Min(1) 2.55 Typ -- Max 2.79 Units V Conditions Param No. BO10 Symbol VBOR Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70318D-page 290 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Program Flash Memory D130 D131 D132B D134 D135 D136a D136b D137a D137b D138a D138b Note 1: 2: EP VPR VPEW TRETD IDDP TRW TRW TPE TPE TWW TWW Cell Endurance VDD for Read VDD for Self-Timed Write Characteristic Retention Supply Current during Programming Row Write Time Row Write Time Page Erase Time Page Erase Time Word Write Cycle Time Word Write Cycle Time 10,000 VMIN VMIN 20 -- 1.32 1.28 20.1 19.5 42.3 41.1 -- -- -- -- 10 -- -- -- -- -- -- -- 3.6 3.6 -- -- 1.74 1.79 26.5 27.3 55.9 57.6 E/W -40C to +125C V V VMIN = Minimum operating voltage VMIN = Minimum operating voltage Min Typ(1) Max Units Conditions Param Symbol No. Year Provided no other specifications are violated, -40C to +125C mA ms ms ms ms s s TRW = 11064 FRC cycles, TA = +85C, See Note 2 TRW = 11064 FRC cycles, TA = +125C, See Note 2 TPE = 168517 FRC cycles, TA = +85C, See Note 2 TPE = 168517 FRC cycles, TA = +125C, See Note 2 TWW = 355 FRC cycles, TA = +85C, See Note 2 TWW = 355 FRC cycles, TA = +125C, See Note 2 Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see Section 5.3 "Programming Operations". TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: Param No. -40C TA +85C for Industrial -40C TA +125C for Extended Characteristics External Filter Capacitor Value Min 4.7 Typ 10 Max -- Units F Comments Capacitor must be low series resistance (< 5 ohms) Symbol CEFC (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 291 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.2 AC Characteristics and Timing Parameters This section defines DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters. TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Operating voltage VDD range as described in Section 24.0 "Electrical Characteristics". AC CHARACTERISTICS FIGURE 24-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 - for OSC2 Load Condition 1 - for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSCO Characteristic OSC2 Pin Min -- Typ -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1 EC mode In I2CTM mode DO56 DO58 CIO CB All I/O Pins and OSC2 SCLx, SDAx -- -- -- -- 50 400 pF pF DS70318D-page 292 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency OS20 OS25 OS30 OS31 OS40 OS41 OS42 Note 1: 2: TOSC TCY TosL, TosH TosR, TosF TckR TckF GM TOSC = 1/FOSC Instruction Cycle Time(2) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time CLKO Rise Time(3) CLKO Fall Time(3) External Oscillator Transconductance(4) Min DC Typ(1) -- Max 40 Units MHz Conditions EC Param No. OS10 Symb FIN 3.5 10 12.5 25 0.375 x TOSC -- -- -- 14 -- -- -- -- -- -- 5.2 5.2 16 10 40 DC DC 0.625 x TOSC 20 -- -- 18 MHz MHz ns ns ns ns ns ns mA/V XT HS EC EC VDD = 3.3V TA = +25C 3: 4: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 293 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Min 0.8 Typ(1) -- Max 8 Units MHz Conditions ECPLL, XTPLL modes Param No. OS50 Symbol FPLLI OS51 OS52 OS53 Note 1: FSYS TLOCK DCLK 100 0.9 -3 -- 1.5 0.5 200 3.1 3 MHz mS % Measured over 100 ms period Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. TABLE 24-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic 0n-Chip 16x PLL CCO Frequency On-Chip 16x PLL Phase Detector Input Frequency Frequency Generator Lock Time Min 105 6.56 -- Typ(1) 120 7.5 -- Max 135 8.44 10 Units MHz MHz s Conditions Param No. Symbol FHPOUT FHPIN TSU Note 1: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. TABLE 24-19: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20 Note 1: 2: FRC FRC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for Extended Min Typ Max Units Conditions Characteristic Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1,2) -- -- 2 5 -- -- % % -40C TA +85C -40C TA +125C VDD = 3.0-3.6V VDD = 3.0-3.6V Frequency calibrated at +25C and 3.3V. TUN bits can be used to compensate for temperature drift. FRC is set to initial frequency of 7.37 MHz (2%) at +25C. DS70318D-page 294 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-20: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F21 LPRC LPRC Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Min Typ Max Units Conditions Characteristic LPRC @ 32.768 kHz(1) -20 -70 6 -- +20 +70 % % -40C TA +85C -40C TA +125C VDD = 3.0-3.6V VDD = 3.0-3.6V Change of LPRC frequency as VDD changes. FIGURE 24-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 24-1 for load conditions. New Value TABLE 24-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time (output) CNx High or Low Time (input) Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions Refer to Figure 24-1 for test conditions Refer to Figure 24-1 for test conditions Param No. DO31 DO32 DI35 DI40 Note 1: Symbol TIOR TIOF TINP TRBP Data in "Typ" column is at 3.3V, +25C unless otherwise stated. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 295 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset SY12 SY10 SY11 SY30 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-1 for load conditions. SY20 SY13 DS70318D-page 296 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) MCLR Pulse Width (low) Power-up Timer Period Min 2 -- Typ(2) -- 2 4 8 16 32 64 128 10 0.72 -- Max -- -- Units s ms Conditions -40C to +85C -40C to +85C User programmable Param Symbol No. SY10 SY11 TMCL TPWRT SY12 SY13 SY20 TPOR TIOZ TWDT1 Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Watchdog Timer Time-out Period 3 0.68 -- 30 1.2 -- s s ms -40C to +85C See Section 21.4 "Watchdog Timer (WDT)" and LPRC parameter F21 (Table 24-20). TOSC = OSC1 period SY30 Note 1: 2: TOST Oscillator Start-up Time -- 1024 TOSC -- -- These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 297 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx15 OS60 TMRx Tx11 Tx20 Note: Refer to Figure 24-1 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA11 TTXL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA15 TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler Asynchronous OS60 Ft1 T1CK Oscillator Input Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) Min 0.5 TCY + 20 10 10 0.5 TCY + 20 10 10 TCY + 40 Greater of: 20 ns or (TCY + 40)/N 20 DC Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns -- N = prescale value (1, 8, 64, 256) Must also meet parameter TA15 Conditions Must also meet parameter TA15 Param No. TA10 Symbol TTXH -- -- -- 50 ns kHz TA20 Note 1: TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Timer1 is a Type A. 0.5 TCY 1.5 TCY -- DS70318D-page 298 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler TB11 TTXL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler TB15 TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 40 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY -- 1.5 TCY -- Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 8, 64, 256) Must also meet parameter TB15 Conditions Must also meet parameter TB15 Param No. TB10 Symbol TTXH TABLE 24-25: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic TxCK High Time TxCK Low Time Synchronous Synchronous Min 0.5 TCY + 20 0.5 TCY + 20 TCY + 40 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY -- 1.5 TCY -- Typ -- -- -- Max -- -- -- Units ns ns ns Conditions Must also meet parameter TC15 Must also meet parameter TC15 N = prescale value (1, 8, 64, 256) Param No. TC10 TC11 TC15 Symbol TTXH TTXL TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 299 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 24-1 for load conditions. IC11 TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) ICx Input Low Time ICx Input High Time ICx Input Period No prescaler With prescaler IC11 IC15 Note 1: TccH TccP No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 (TCY + 40)/N Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4, 16) Conditions Param No. IC10 Symbol TccL These parameters are characterized but not tested in manufacturing. FIGURE 24-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 24-1 for load conditions. TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Min -- -- Typ -- -- Max -- -- Units ns ns Conditions See parameter D032 See parameter D031 Param Symbol No. OC10 OC11 Note 1: TccF TccR Characteristic(1) OCx Output Fall Time OCx Output Rise Time These parameters are characterized but not tested in manufacturing. DS70318D-page 300 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx TABLE 24-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) Fault Input to PWM I/O Change Fault Input Pulse Width Min -- 50 Typ -- -- Max 50 -- Units ns ns Conditions Param No. OC15 OC20 Note 1: Symbol TFD TFLT These parameters are characterized but not tested in manufacturing. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 301 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-9: HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 24-10: HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 24-1 for load conditions. TABLE 24-29: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) PWM Output Fall Time PWM Output Rise Time Fault Input to PWM I/O Change Minimum Pulse Width Tap Delay PWM Input Clock Min -- -- -- -- -- -- Typ 2.5 2.5 -- 8 1.04 -- Max -- -- 15 -- -- 120 Units ns ns ns ns ns MHz ACLK = 120 MHz Conditions See parameter D032 See parameter D031 Param No. MP10 MP11 MP20 MP30 Symbol TFPWM TRPWM TFD TFH TPDLY ACLK Note 1: These parameters are characterized but not tested in manufacturing. DS70318D-page 302 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-11: SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 MSb SP31 SDIx MSb In SP40 SP41 Bit 14 - - - -1 Bit 14 - - - - - -1 SP30 LSb In SP21 LSb SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SDOx Note: Refer to Figure 24-1 for load conditions. TABLE 24-30: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Output Low Time SCKx Output High Time SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Min TCY/2 TCY/2 -- -- -- -- -- 23 30 Typ(2) -- -- -- -- -- -- 6 -- -- Max -- -- -- -- -- -- 20 -- -- Units ns ns ns ns ns ns ns ns ns Conditions See Note 3 See Note 3 See parameter D032 and Note 4 See parameter D031 and Note 4 See parameter D032 and Note 4 See parameter D031 and Note 4 Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4: Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL TscH2diL, TscL2diL These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 303 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-12: SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SP35 SP20 LSb SP21 SDOX MSb SP40 Bit 14 - - - - - -1 SP30,SP31 Bit 14 - - - -1 SDIX MSb In SP41 LSb In Note: Refer to Figure 24-1 for load conditions. TABLE 24-31: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Output Low Time SCKx Output High Time SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge SDOx Data Output Setup to First SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Min TCY/2 TCY/2 -- -- -- -- -- 30 23 30 Typ(2) -- -- -- -- -- -- 6 -- -- -- Max -- -- -- -- -- -- 20 -- -- -- Units ns ns ns ns ns ns ns ns ns ns Conditions See Note 3 See Note 3 See parameter D032 and Note 4 See parameter D031 and Note 4 See parameter D032 and Note 4 See parameter D031 and Note 4 Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4: Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdoV2sc, TdoV2scL TdiV2scH, TdiV2scL TscH2diL, TscL2diL These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70318D-page 304 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-13: SSX SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX MSb In SP41 Bit 14 - - - -1 SP40 Note: Refer to Figure 24-1 for load conditions. TABLE 24-32: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx to SCKx or SCKx Input SSx to SDOx Output High-Impedance Min 30 30 -- -- -- -- -- 20 20 120 10 Typ(2) -- -- 10 10 -- -- -- -- -- -- -- Max -- -- 25 25 -- -- 30 -- -- -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns See Note 3 Conditions Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ See Note 3 See Note 3 See parameter D032 and Note 3 See parameter D031 and Note 3 TscH2ssH SSx after SCKx Edge 1.5 TCY +40 -- -- TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. 3: Assumes 50 pF load on all SPIx pins. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 305 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-14: SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP52 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI MSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. Bit 14 - - - -1 LSb In SP72 LSb SP51 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 DS70318D-page 306 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-33: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min 30 30 -- -- -- -- -- 20 20 120 10 1.5 TCY + 40 -- Typ(2) -- -- 10 10 -- -- -- -- -- -- -- -- -- Max -- -- 25 25 -- -- 30 -- -- -- 50 -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns See Note 4 See Note 3 See Note 3 See parameter D032 and Note 3 See parameter D031 and Note 3 Conditions Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 SP60 Note 1: 2: 3: 4: Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ TscH2ssH TscL2ssH TssL2doV Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx to SCKx or SCKx Input SSx to SDOX Output High-Impedance SSx after SCKx Edge SDOx Data Output Valid after SSx Edge These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 307 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM30 SDAx IM33 IM34 Start Condition Note: Refer to Figure 24-1 for load conditions. Stop Condition FIGURE 24-16: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM11 IM26 IM21 SCLx IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 24-1 for load conditions. DS70318D-page 308 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-34: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min(1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 40 0 0 0.2 TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) -- -- -- 4.7 1.3 0.5 -- Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 1000 400 -- -- -- 400 Units s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns ns ns ns s s s pF Time the bus must be free before a new transmission can start Only relevant for Repeated Start condition After this period the first clock pulse is generated CB is specified to be from 10 pF to 400 pF CB is specified to be from 10 pF to 400 pF Conditions Param Symbol No. IM10 TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (2) IM11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(2) IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode (2) IM21 TR:SCL IM25 TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time IM26 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode (2) IM30 IM31 THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time IM33 IM34 IM40 TAA:SCL Output Valid From Clock IM45 TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode(2) IM50 Note 1: 2: CB Bus Capacitive Loading BRG is the value of the I2CTM Baud Rate Generator. Refer to Section 19. "Inter-Integrated Circuit (I2CTM)" (DS70195) in the "dsPIC33F Family Reference Manual" available from the Microchip web site. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 309 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-17: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 IS33 IS34 SDAx Start Condition Stop Condition FIGURE 24-18: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70318D-page 310 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-35: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS20 TF:SCL SDAx and SCLx Fall Time SDAx and SCLx Rise Time Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS21 TR:SCL 100 kHz mode 400 kHz mode 1 MHz mode(1) IS25 TSU:DAT 100 kHz mode 400 kHz mode 1 MHz mode(1) IS26 THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode IS30 (1) Param. Symbol IS10 TLO:SCL Min 4.7 1.3 0.5 4.0 0.6 0.5 -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 4.7 0.6 0.25 4.0 0.6 0.25 4.7 0.6 0.6 4000 600 250 0 0 0 4.7 1.3 0.5 -- Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- 3500 1000 350 -- -- -- 400 Units s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns ns ns ns s s s pF Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz CB is specified to be from 10 pF to 400 pF CB is specified to be from 10 pF to 400 pF 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode (1) Only relevant for Repeated Start condition After this period, the first clock pulse is generated IS31 THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time IS33 IS34 THD:STO Stop Condition Hold Time TAA:SCL Output Valid From Clock IS40 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS45 TBF:SDA Bus Free Time Time the bus must be free before a new transmission can start IS50 Note 1: CB Bus Capacitive Loading Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 311 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 = TABLE 24-36: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions: 3.0V and 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min. Typ Max. Units Conditions Param No. AD01 AD02 AD10 AD11 AD12 AD13 Symbol Device Supply AVDD AVSS Module VDD Supply Module VSS Supply -- -- VSS AVSS -- -- 8 0.6 -- -- -- -- VDD AVDD -- -- -- -- V V mA A VINL = AVSS = 0V, AVDD = 3.3V Source Impedance = 100 See the VDD specification (DC10) in Table 24-4 AVSS is connected to VSS Analog Input VINH-VINL Full-Scale Input Span VIN IAD -- Absolute Input Voltage Operating Current Leakage Current AD17 RIN Recommended Impedance Of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Input Signal Bandwidth Effective Number of Bits -- DC Accuracy 100 AD20 Nr 10 data bits -- -- -- -- -- -- -- -- -- -- 0.5 0.5 0.75 2.0 -- -73 58 -73 -- 9.4 <2 <1 <3.0 <5.0 -- -- -- -- 0.5 -- bits LSb See Note 2 LSb See Note 2 LSb See Note 2 LSb See Note 2 -- dB dB dB MHz bits Guaranteed AD21A INL AD22A DNL AD23A GERR AD24A EOFF AD25 AD30 AD31 AD32 AD33 AD34 Note 1: 2: -- THD SINAD SFDR FNYQ ENOB Dynamic Performance The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. This parameter is characterized under the following conditions: AVDD = 3.3V, 2.0 MSPS for dedicated S/H, 1.5 MSPS for shared S/H. This parameter is not tested in manufacturing. DS70318D-page 312 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-37: 10-BIT HIGH-SPEED A/D MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min. Typ(1) Max. Units Conditions Param Symbol No. AD50b TAD AD55b tCONV AD56b FCNV Clock Parameters ADC Clock Period Conversion Time Throughput Rate Devices with Single SAR Devices with Dual SARs AD63b tDPU Note 1: Time to Stabilize Analog Stage from ADC Off to ADC On(1) -- -- 1.0 -- -- -- 2.0 4.0 10 Msps Msps s 35.8 -- -- 14 TAD -- -- ns -- Conversion Rate Timing Parameters These parameters are characterized but not tested in manufacturing. FIGURE 24-19: A/D CONVERSION TIMING PER INPUT Tconv Trigger Pulse TAD A/D Clock A/D Data ADBUFxx CONV 9 Old Data 8 2 1 0 New Data (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 313 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-38: COMPARATOR AC AND DC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Param. Symbol Characteristic No. VIOFF VICM VGAIN CMRR TRESP Input Offset Voltage Input Common Mode Voltage Range(1) Open Loop Gain(1) Common Mode Rejection Ratio(1) Large Signal Response 0 90 70 Min Typ 5 -- -- -- 20 Max 15 AVDD - 1.5 -- -- 30 Units mV V db db ns V+ input step of 100 mv while V- input held at AVDD/2. Delay measured from analog input pin to PWM output pin. Comments Note 1: Parameters are for design guidance only and are not tested in manufacturing. TABLE 24-39: DAC DC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Param. Symbol Characteristic No. CVRSRC External Reference Voltage(1) CVRES INL DNL EOFF EG Note 1: Resolution Transfer Function Accuracy Integral Nonlinearity Error Differential Nonlinearity Error Offset Error Gain Error -- -- -- -- Min 0 10 1.0 0.8 2.0 2.0 -- -- -- -- Typ Max AVDD - 1.6 Units V Bits LSB LSB LSB LSB AVDD = 3.3V, DACREF = (AVDD/2)V Comments Parameters are for design guidance only and are not tested in manufacturing. TABLE 24-40: DAC AC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Param. No. Symbol Characteristic TSET Settling Time(1) Min Typ Max 650 Units nsec Comments Measured when range = 1 (high range), and CMREF<9:0> transitions from 0x1FF to 0x300. Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70318D-page 314 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-41: DAC OUTPUT BUFFER DC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Param Symbol Characteristic No. RLOAD CLOAD IOUT VRANGE Resistive Output Load Impedance Output Load Capacitance Output Current Drive Strength Full Output Drive Strength Voltage Range Min 3K -- 200 AVSS + 250 mV AVSS + 50 mV Typ -- 20 300 -- -- Max -- 35 400 AVDD - 900 mV AVDD - 500 mV 1.3 x IOUT Units pF A V V Sink and source Comments VLRANGE Output Drive Voltage Range at Reduced Current Drive of 50 A IDD Current Consumed when Module is Enabled, High-Power Mode -- -- A Module will always consume this current even if no load is connected to the output Closed loop output resistance buf_enable = 0 RIN Input Impedance 109 -- 107 -- -- -- -- 10 -- ROUTON Output Impedance when Module is Enabled ROUTOFF Output Impedance when Module is Disabled (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 315 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 316 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.0 PACKAGING INFORMATION 18-Lead SOIC (.300") XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example dsPIC33FJ06 GS101-I/SO e3 0830235 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example dsPIC33FJ06GS 202-E/SO e3 0830235 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example dsPIC33FJ06GS 202-E/SP e3 0830235 Legend: XX...X Y YY WW NNN * e3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 317 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.1 Package Marking Information (Continued) 28-Lead QFN-S Example XXXXXXXX XXXXXXXX YYWWNNN 33FJ06GS 202EMM e3 0830235 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33FJ16 GS504-E/ML e3 0830235 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33FJ 16GS504 -E/PT e3 0830235 DS70318D-page 318 Preliminary (c) 2009 Microchip Technology Inc. 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DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 327 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 328 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 APPENDIX A: REVISION HISTORY Revision B (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. In addition, redundant information was removed that is now available in the respective chapters of the dsPIC33F Family Reference Manual, which can be obtained from the Microchip website (www.microchip.com). The major changes are referenced by their respective section in the following table. Revision A (January 2008) This is the initial revision of this document. TABLE A-1: MAJOR SECTION UPDATES Update Description Moved location of Note 1 (RP# pin) references (see "Pin Diagrams"). Updated CPU Core Register map SFR reset value for CORCON (see Table 3-1). Removed Interrupt Controller Register Map SFR IPC29 and updated reset values for IPC0, IPC1, IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table 3-5). Removed Interrupt Controller Register Map SFR IPC24 and IPC29 and updated reset values for IPC0, IPC1, IPC2, IPC14, IPC16, IPC23, IPC27, and IPC28 (see Table 3-6). Removed Interrupt Controller Register Map SFR IPC24 and updated reset values for IPC1, IPC2, IPC4, IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table 3-7). Updated Interrupt Controller Register Map SFR reset values for IPC1, IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table 3-8). Updated Interrupt Controller Register Map SFR reset values for IPC1, IPC14, IPC16, IPC23, IPC24, IPC25, IPC26, IPC27, IPC28, and IPC29 (see Table 3-9). Updated Interrupt Controller Register Map SFR reset values for IPC1, IPC4, IPC14, IPC16, IPC23, IPC24, IPC25, IPC26, IPC27, IPC28, and IPC29 (see Table 3-10). Added SFR definitions for RPOR16 and RPOR17 (see Table 3-34, Table 3-35, and Table 3-36). Updated bit definitions for PORTA, PORTB, and PORTC SFRs (ODCA, ODCB, and ODCC) (see Table 3-37, Table 3-38, Table 3-39, and Table 3-40). Updated bit definitions and reset value for System Control Register map SFR CLKDIV (see Table 3-41). Added device-specific information to title of PMD Register Map (see Table 3-47). Added device-specific PMD Register Maps (see Table 3-46, Table 3-45, and Table 3-43). Section Name "High-Performance, 16-Bit Digital Signal Controllers" Section 3.0 "Memory Organization" (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 329 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Removed the first sentence of the third clock source item (External Clock) in Section 7.1.1 "System Clock sources" Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register 7-2). Section 8.0 "Power-Saving Features" Added the following six registers: * "PMD1: Peripheral Module Disable Control Register 1" * "PMD2: Peripheral Module Disable Control Register 2" * "PMD3: Peripheral Module Disable Control Register 3" * "PMD4: Peripheral Module Disable Control Register 4" * "PMD6: Peripheral Module Disable Control Register 6" * "PMD7: Peripheral Module Disable Control Register 7" Added paragraph and Table 9-1 to Section 9.1.1 "Open-Drain Configuration", which provides details on I/O pins and their functionality. Removed 9.1.2 "5V Tolerance". Updated MUX range and removed virtual pin details in Figure 9-2. Updated PWM Input Name descriptions in Table 9-1. Added Section 9.4.2.3 "Virtual Pins". Updated bit values in all Peripheral Pin Select Input Registers (see Register 9-1 through Register 9-14). Updated bit name information for Peripheral Pin Select Output Registers RPOR16 and RPOR17 (see Register 9-30 and Register 9-31). Added the following two registers: * "RPOR16: Peripheral Pin Select Output Register 16" * "RPOR17: Peripheral Pin Select Output Register 17" Removed the following sections: * 9.4.2 "Available Peripherals" * 9.4.3.2 "Virtual Input Pins" * 9.4.3.4 "Peripheral Mapping" * 9.4.5 "Considerations for Peripheral Pin Selection" (and all subsections) Section 14.0 "High-Speed PWM" Added Note 1 (remappable pin reference) to Figure 14-1. Added Note 2 (Duty Cycle resolution) to PWM Master Duty Cycle Register (Register 14-5), PWM Generator Duty Cycle Register (Register 14-7), and PWM Secondary Duty Cycle Register (Register 14-8). Added Note 2 and Note 3 and updated bit information for CLSRC and FLTSRC in the PWM Fault Current-Limit Control Register (Register 14-15). Section 15.0 "Serial Peripheral Interface (SPI)" Removed the following sections, which are now available in the related section of the dsPIC33F Family Reference Manual: * 15.1 "Interrupts" * 15.2 "Receive Operations" * 15.3 "Transmit Operations" * 15.4 "SPI Setup" (retained Figure 15-1: SPI Module Block Diagram) Section Name Section 7.0 "Oscillator Configuration" Section 9.0 "I/O Ports" DS70318D-page 330 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Removed the following sections, which are now available in the related section of the dsPIC33F Family Reference Manual: * 16.3 "I2C Interrupts" * 16.4 "Baud Rate Generator" (retained Figure 16-1: I2C Block Diagram) * 16.5 "I2C Module Addresses * 16.6 "Slave Address Masking" * 16.7 "IPMI Support" * 16.8 "General Call Address Support" * 16.9 "Automatic Clock Stretch" * 16.10 "Software Controlled Clock Stretching (STREN = 1)" * 16.11 "Slope Control" * 16.12 "Clock Arbitration" * 16.13 "Multi-Master Communication, Bus Collision, and Bus Arbitration Section Name Section 16.0 "Inter-Integrated Circuit (I2CTM)" Section 17.0 "Universal Removed the following sections, which are now available in the related Asynchronous Receiver Transmitter section of the dsPIC33F Family Reference Manual: (UART)" * 17.1 "UART Baud Rate Generator" * 17.2 "Transmitting in 8-bit Data Mode * 17.3 "Transmitting in 9-bit Data Mode * 17.4 "Break and Sync Transmit Sequence" * 17.5 "Receiving in 8-bit or 9-bit Data Mode" * 17.6 "Flow Control Using UxCTS and UxRTS Pins" * 17.7 "Infrared Support" Removed IrDA references and Note 1, and updated the bit and bit value descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control Register (see Register 17-2). Section 18.0 "High-Speed 10-bit Analog-to-Digital Converter (ADC)" Updated bit value information for A/D Control Register (see Register 18-1). Updated TRGSRC6 bit value for Timer1 period match in the A/D Convert Pair Control Register 3 (see Register 18-8). (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 331 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Updated Typ values for Thermal Packaging Characteristics (Table 23-3). Removed Typ value for DC Temperature and Voltage Specifications parameter DC12 (Table 23-4). Updated all Typ values and conditions for DC Characteristics: Operating Current (IDD), updated last sentence in Note 2 (Table 23-5). Updated all Typ values for DC Characteristics: Idle Current (IIDLE) (see Table 23-6). Updated all Typ values for DC Characteristics: Power Down Current (IPD) (see Table 23-7). Updated all Typ values for DC Characteristics: Doze Current (IDOZE) (see Table 23-8). Added Note 4 (reference to new table containing digital-only and analog pin information, as well as Current Sink/Source capabilities) in the I/O Pin Input Specifications (Table 23-9). Updated Max value for BOR electrical characteristics parameter BO10 (see Table 23-11). Swapped Min and Typ values for Program Memory parameters D136 and D137 (Table 23-12). Updated Typ values for Internal RC Accuracy parameter F20 and added Extended temperature range to table heading (see Table 23-19). Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and Power-up Timer parameter SY20 and updated conditions, which now refers to Section 20.4 "Watchdog Timer (WDT)" and LPRC parameter F21 (see Table 23-22). Added specifications to High-Speed PWM Module Timing Requirements for Tap Delay (Table 23-29). Updated Min and Max values for 10-bit High-Speed A/D Module parameters AD01 and AD11 (see Table 23-36). Updated Max value and unit of measure for DAC AC Specification (see Table 23-40). Section Name Section 23.0 "Electrical Characteristics" DS70318D-page 332 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision C and D (March 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: * Changed all instances of OSCI to OSC1 and OSCO to OSC2 * Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2, or 3) to PGECx and PGEDx * Changed all instances of VDDCORE and VDDCORE/ VCAP to VCAP/VDDCORE Other major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Update Description Added "Application Examples" to list of features Updated all pin diagrams to denote the pin voltage tolerance (see "Pin Diagrams"). Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section Name "High-Performance, 16-Bit Digital Signal Controllers" Section 1.0 "Device Overview" Section 2.0 "Guidelines for Getting Started with 16-bit Digital Signal Controllers" Section 3.0 "CPU" Added ACMP1-ACMP4 pin names and Peripheral Pin Select capability column to Pinout I/O Descriptions (see Table 1-1). Added new section to the data sheet that provides guidelines on getting started with 16-bit Digital Signal Controllers. Updated CPU Core Block Diagram with a connection from the DSP Engine to the Y Data Bus (see Figure 3-1). Vertically extended the X and Y Data Bus lines in the DSP Engine Block Diagram (see Figure 3-3). Section 4.0 "Memory Organization" Updated Reset value for ADCON in Table 4-25. Removed reference to dsPIC33FJ06GS102 devices in the PMD Register Map and updated bit definitions for PMD1 and PMD6, and removed PMD7 (see Table 4-43). Added a new PMD Register Map, which references dsPIC33FJ06GS102 devices (see Table 4-44). Updated RAM stack address and SPLIM values in the third paragraph of Section 4.2.6 "Software Stack" Removed Section 4.2.7 "Data Ram Protection Feature". Section 5.0 "Flash Program Memory" Updated Section 5.3 "Programming Operations" with programming time formula. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 333 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Update Description Added Note 2 to the Oscillator System Diagram (see Figure 8-1). Added a paragraph regarding FRC accuracy at the end of Section 8.1.1 "System Clock Sources". Added Note 1 and Note 2 to the OSCON register (see Register ). Added Note 1 to the OSCTUN register (see Register 8-4). Added Note 3 to Section 8.4.2 "Oscillator Switching Sequence". Section 10.0 "I/O Ports" Removed Table 9-1 and added reference to pin diagrams for I/O pin availability and functionality. Added paragraph on ADPCFG register default values to Section 10.2 "Configuring Analog Port Pins". Added Note box regarding PPS functionality with input mapping to Section 10.4.2.1 "Input Mapping". Section 15.0 "High-Speed PWM" Updated Note 2 in the PTCON register (see Register 15-1). Added Note 4 to the PWMCONx register (see Register 15-6). Updated Notes for the PHASEx and SPHASEx registers (see Register 15-9 and Register 15-10, respectively). Section 16.0 "Serial Peripheral Interface (SPI)" Added Note 2 and Note 3 to the SPIxCON1 register (see Register 16-2). Section Name Section 8.0 "Oscillator Configuration" Section 18.0 "Universal Updated the Notes in the UxMode register (see Register 18-1). Asynchronous Receiver Transmitter Updated the UTXINV bit settings in the UxSTA register and added Note 1 (UART)" (see Register 18-2). Section 19.0 "High-Speed 10-bit Analog-to-Digital Converter (ADC)" Updated the SLOWCLK and ADCS<2:0> bit settings and updated Note 1in the ADCON register (see Register 19-1). Removed all notes in the ADPCFG register and replaced them with a single note (see Register 19-4). Updated the SWTRGx bit settings in the ADCPCx registers (see Register 19-5, Register 19-6, Register 19-7, and Register 19-8). DS70318D-page 334 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Update Description Updated Typical values for Thermal Packaging Characteristics (see Table 24-3). Updated Min and Max values for parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table 24-4). Updated Characteristics for I/O Pin Input Specifications (see Table 24-9). Added ISOURCE to I/O Pin Output Specifications (see Table 24-10). Updated Program Memory values for parameters 136, 137, and 138 (renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and 138b, and added Note 2 (see Table 24-12). Added parameter OS42 (GM) to the External Clock Timing Requirements (see Table 24-16). Updated Conditions for symbol TPDLY (Tap Delay) and added symbol ACLK (PWM Input Clock) to the High-Speed PWM Module Timing Requirements (see Table 24-29). Updated parameters AD01 and AD02 in the 10-bit High-Speed A/D Module Specifications (see Table 24-36). Updated parameters AD50b, AD55b, and AD56b, and removed parameters AD57b and AD60b from the 10-bit High-Speed A/D Module Timing Requirements (see Table 24-37). Section Name Section 24.0 "Electrical Characteristics" (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 335 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318D-page 336 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INDEX Numerics 10-bit High Speed Analog-to-Digital Converter. See A/D CPU Control Registers........................................................ 24 CPU Clocking System ...................................................... 128 PLL Configuration..................................................... 129 Selection................................................................... 128 Sources .................................................................... 128 Customer Change Notification Service............................. 331 Customer Notification Service .......................................... 331 Customer Support............................................................. 331 A A/D .................................................................................... 229 AC Characteristics ............................................................ 284 Internal RC Accuracy ................................................ 286 Load Conditions ........................................................ 284 Alternate Vector Table (AIVT) ............................................. 87 Arithmetic Logic Unit (ALU)................................................. 27 Assembler MPASM Assembler................................................... 272 D DAC .................................................................................. 252 Output Range ........................................................... 252 Data Accumulators and Adder/Subtracter .......................... 29 Data Space Write Saturation ...................................... 31 Overflow and Saturation ............................................. 29 Round Logic ............................................................... 30 Write Back .................................................................. 30 Data Address Space........................................................... 35 Alignment.................................................................... 35 Memory Map for DSPIC33FJ06GS101/102 Devices with 256 Bytes of RAM ....................................... 36 Memory Map for dsPIC33FJ06GS202 Device with 1-Kbyte RAM............................................... 37 Memory Map for dsPIC33FJ16GS402/404/502/504 Devices with 2-Kbyte RAM ................................. 38 Near Data Space ........................................................ 35 Software Stack ........................................................... 63 Width .......................................................................... 35 DC Characteristics............................................................ 276 Doze Current (IDOZE)................................................ 280 I/O Pin Input Specifications ...................................... 281 I/O Pin Output Specifications.................................... 282 Idle Current (IIDLE) .................................................... 279 Operating Current (IDD) ............................................ 278 Power-Down Current (IPD)........................................ 280 Program Memory...................................................... 283 Temperature and Voltage Specifications.................. 277 Development Support ....................................................... 271 Doze Mode ....................................................................... 138 DSP Engine ........................................................................ 27 Multiplier ..................................................................... 29 B Barrel Shifter ....................................................................... 31 Bit-Reversed Addressing .................................................... 66 Example ...................................................................... 67 Implementation ........................................................... 66 Sequence Table (16-Entry)......................................... 67 Block Diagrams 16-Bit Timer1 Module................................................ 175 Comparator ............................................................... 251 Connections for On-Chip Voltage Regulator............. 258 DSP Engine ................................................................ 28 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU Core.................. 22 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ................................... 14 I2C............................................................................. 216 Input Capture ............................................................ 183 Oscillator System ...................................................... 127 Output Compare ....................................................... 185 PLL............................................................................ 129 Reset System.............................................................. 79 Shared Port Structure ............................................... 145 Simplified Conceptual High-Speed PWM ................. 190 SPI ............................................................................ 209 Timer2/3 (32-Bit) ....................................................... 179 Type B Timer ............................................................ 177 Type C Timer ............................................................ 177 UART ........................................................................ 223 Watchdog Timer (WDT) ............................................ 259 Brown-out Reset (BOR) .................................................... 255 E EBCONx (Leading-Edge Blanking Control) ...................... 207 Electrical Characteristics .................................................. 275 AC Characteristics and Timing Parameters ............. 284 BOR.......................................................................... 282 Equations Device Operating Frequency.................................... 128 FOSC Calculation ...................................................... 129 XT with PLL Mode Example ..................................... 129 Errata .................................................................................. 12 C C Compilers MPLAB C18 .............................................................. 272 MPLAB C30 .............................................................. 272 Clock Switching................................................................. 136 Enabling .................................................................... 136 Sequence.................................................................. 136 Code Examples Erasing a Program Memory Page............................... 77 Initiating a Programming Sequence............................ 78 Loading Write Buffers ................................................. 78 Port Write/Read ........................................................ 147 PWRSAV Instruction Syntax..................................... 137 Code Protection ........................................................ 255, 261 CodeGuard Security ......................................................... 255 Configuration Bits.............................................................. 255 Configuration Register Map .............................................. 255 Configuring Analog Port Pins ............................................ 147 F Fail-Safe Clock Monitor (FSCM)....................................... 136 Flash Program Memory ...................................................... 73 Control Registers........................................................ 74 Operations .................................................................. 74 Programming Algorithm .............................................. 77 RTSP Operation ......................................................... 74 Table Instructions ....................................................... 73 Flexible Configuration ....................................................... 255 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 337 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 H High-Speed Analog Comparator ....................................... 251 High-Speed PWM ............................................................. 189 MPLAB Integrated Development Environment Software.. 271 MPLAB PM3 Device Programmer .................................... 273 MPLAB REAL ICE In-Circuit Emulator System ................ 273 MPLINK Object Linker/MPLIB Object Librarian ................ 272 I I/O Ports ............................................................................ 145 Parallel I/O (PIO)....................................................... 145 Write/Read Timing .................................................... 147 I2C Operating Modes ...................................................... 215 Registers ................................................................... 215 In-Circuit Debugger ........................................................... 260 In-Circuit Emulation........................................................... 255 In-Circuit Serial Programming (ICSP) ....................... 255, 260 Input Capture .................................................................... 183 Registers ................................................................... 184 Input Change Notification.................................................. 147 Instruction Addressing Modes............................................. 63 File Register Instructions ............................................ 63 Fundamental Modes Supported.................................. 64 MAC Instructions......................................................... 64 MCU Instructions ........................................................ 63 Move and Accumulator Instructions ............................ 64 Other Instructions........................................................ 64 Instruction Set Overview ................................................................... 266 Summary................................................................... 263 Instruction-Based Power-Saving Modes ........................... 137 Idle ............................................................................ 138 Sleep ......................................................................... 137 Interfacing Program and Data Memory Spaces .................. 68 Internal RC Oscillator Use with WDT ........................................................... 259 Internet Address................................................................ 331 Interrupt Control and Status Registers................................ 91 IECx ............................................................................ 91 IFSx............................................................................. 91 INTCON1 .................................................................... 91 INTCON2 .................................................................... 91 INTTREG .................................................................... 91 IPCx ............................................................................ 91 Interrupt Setup Procedures ............................................... 125 Initialization ............................................................... 125 Interrupt Disable........................................................ 125 Interrupt Service Routine .......................................... 125 Trap Service Routine ................................................ 125 Interrupt Vector Table (IVT) ................................................ 87 Interrupts Coincident with Power Save Instructions.......... 138 O Open-Drain Configuration................................................. 146 Oscillator Configuration .................................................... 127 Output Compare ............................................................... 185 P Packaging ......................................................................... 309 Details....................................................................... 311 Marking ..................................................................... 309 Peripheral Module Disable (PMD) .................................... 138 PICSTART Plus Development Programmer..................... 274 Pinout I/O Descriptions (table)............................................ 15 Power-on Reset (POR)....................................................... 84 Power-Saving Features .................................................... 137 Clock Frequency and Switching ............................... 137 Program Address Space..................................................... 33 Construction ............................................................... 68 Data Access from Program Memory Using Program Space Visibility..................................... 71 Data Access from Program Memory Using Table Instructions ............................................... 70 Data Access from, Address Generation ..................... 69 Memory Maps ............................................................. 33 Table Read Instructions TBLRDH ............................................................. 70 TBLRDL.............................................................. 70 Visibility Operation ...................................................... 71 Program Memory Interrupt Vector ........................................................... 34 Organization ............................................................... 34 Reset Vector ............................................................... 34 R Reader Response............................................................. 332 Registers .................................................................................. 207 A/D Control Register (ADCON) ................................ 237 A/D Convert Pair Control Register 0 (ADCPC0)....... 241 A/D Convert Pair Control Register 1 (ADCPC1)....... 243 A/D Convert Pair Control Register 2 (ADCPC2)....... 246 A/D Convert Pair Control Register 3 (ADCPC3)....... 249 A/D Port Configuration Register (ADPCFG) ............. 240 A/D Status Register (ADSTAT)................................. 239 ACLKCON (Auxiliary Clock Divisor Control)............. 134 ALTDTRx (PWM Alternate Dead-Time).................... 200 CLKDIV (Clock Divisor) ............................................ 131 CMPCPNx (Comparator Control) ............................. 253 CMPDACx (Comparator DAC Control)..................... 254 CORCON (Core Control) ...................................... 26, 92 DTRx (PWMx Dead-Time)........................................ 200 FCLCONx (PWMx Fault Current-Limit Control)........ 204 I2CxCON (I2Cx Control) ........................................... 217 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 221 I2CxSTAT (I2Cx Status) ........................................... 219 ICxCON (Input Capture x Control)............................ 184 IEC0 (Interrupt Enable Control 0) ............................. 103 IEC1 (Interrupt Enable Control 1) ............................. 105 IEC3 (Interrupt Enable Control 3) ............................. 106 IEC4 (Interrupt Enable Control 4) ............................. 106 IEC5 (Interrupt Enable Control 5) ............................. 107 IFS0 (Interrupt Flag Status 0) ..................................... 96 J JTAG Boundary Scan Interface ........................................ 255 JTAG Interface .................................................................. 260 M Memory Organization.......................................................... 33 Microchip Internet Web Site .............................................. 331 Modulo Addressing ............................................................. 65 Applicability ................................................................. 66 Operation Example ..................................................... 65 Start and End Address ................................................ 65 W Address Register Selection .................................... 65 MPLAB ASM30 Assembler, Linker, Librarian ................... 272 MPLAB ICD 2 In-Circuit Debugger.................................... 273 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 273 DS70318D-page 338 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 IFS1 (Interrupt Flag Status 1) ..................................... 98 IFS3 (Interrupt Flag Status 3) ..................................... 99 IFS4 (Interrupt Flag Status 4) ..................................... 99 IFS5 (Interrupt Flag Status 5) ................................... 100 IFS6 (Interrupt Flag Status 6) ........................... 101, 108 IFS7 (Interrupt Flag Status 7) ........................... 102, 109 INTCON1 (Interrupt Control 1).................................... 93 INTTREG Interrupt Control and Status ..................... 124 IOCONx (PWMx I/O Control) .................................... 202 IPC0 (Interrupt Priority Control 0) ............................. 110 IPC1 (Interrupt Priority Control 1) ............................. 111 IPC14 (Interrupt Priority Control 14) ......................... 116 IPC16 (Interrupt Priority Control 16) ......................... 116 IPC2 (Interrupt Priority Control 2) ............................. 112 IPC23 (Interrupt Priority Control 23) ......................... 117 IPC24 (Interrupt Priority Control 24) ......................... 118 IPC25 (Interrupt Priority Control 25) ......................... 119 IPC26 (Interrupt Priority Control 26) ......................... 120 IPC27 (Interrupt Priority Control 27) ......................... 121 IPC28 (Interrupt Priority Control 28) ......................... 122 IPC29 (Interrupt Priority Control 29) ......................... 123 IPC3 (Interrupt Priority Control 3) ............................. 113 IPC4 (Interrupt Priority Control 4) ............................. 114 IPC5 (Interrupt Priority Control 5) ............................. 115 IPC7 (Interrupt Priority Control 7) ............................. 115 MDC (PWM Master Duty Cycle) ............................... 194 NVMCON (Flash Memory Control) ............................. 75 NVMKEY (Nonvolatile Memory Key) .......................... 76 OCxCON (Output Compare x Control) ..................... 187 OSCCON (Oscillator Control) ................................... 130 OSCTUN (Oscillator Tuning) .................................... 133 PLLFBD (PLL Feedback Divisor).............................. 132 PMD1 (Peripheral Module Disable Control 1)........... 139 PMD2 (Peripheral Module Disable Control 2)........... 140 PMD3 (Peripheral Module Disable Control 3)........... 141 PMD4 (Peripheral Module Disable Control 4)........... 141 PMD6 (Peripheral Module Disable Control 6)........... 142 PMD7 (Peripheral Module Disable Control 7)........... 143 PTCON (PWM Time Base Control) .......................... 192 PWMCAPx (Primary PWMx Time Base Capture)..... 208 PWMCONx (PWMx Control)..................................... 195 RCON (Reset Control) ................................................ 80 REFOCON (Reference Oscillator Control) ............... 135 RPINR0 (Peripheral Pin Select Input 0).................... 152 RPINR1 (Peripheral Pin Select Input 1).................... 153 RPINR11 (Peripheral Pin Select Input 11)................ 156 RPINR18 (Peripheral Pin Select Input 18)................ 157 RPINR20 (Peripheral Pin Select Input 20)................ 158 RPINR21 (Peripheral Pin Select Input 21)................ 159 RPINR29 (Peripheral Pin Select Input 29)................ 160 RPINR3 (Peripheral Pin Select Input 3).................... 154 RPINR30 (Peripheral Pin Select Input 30)................ 161 RPINR31 (Peripheral Pin Select Input 31)................ 162 RPINR32 (Peripheral Pin Select Input 32)................ 163 RPINR33 (Peripheral Pin Select Input 33)................ 164 RPINR34 (Peripheral Pin Select Input 34)................ 165 RPINR7 (Peripheral Pin Select Input 7).................... 155 RPOR0 (Peripheral Pin Select Output 0).................. 165 RPOR1 (Peripheral Pin Select Output 1).................. 166 RPOR10 (Peripheral Pin Select Output 10).............. 170 RPOR11 (Peripheral Pin Select Output 11).............. 171 RPOR12 (Peripheral Pin Select Output 12).............. 171 RPOR13 (Peripheral Pin Select Output 13).............. 172 RPOR14 (Peripheral Pin Select Output 14).............. 172 RPOR16 (Peripheral Pin Select Output 16).............. 173 RPOR17 (Peripheral Pin Select Output 17).............. 173 RPOR2 (Peripheral Pin Select Output 2) ................. 166 RPOR3 (Peripheral Pin Select Output 3) ................. 167 RPOR4 (Peripheral Pin Select Output 4) ................. 167 RPOR5 (Peripheral Pin Select Output 5) ................. 168 RPOR6 (Peripheral Pin Select Output 6) ................. 168 RPOR7 (Peripheral Pin Select Output 7) ................. 169 RPOR8 (Peripheral Pin Select Output 8) ................. 169 RPOR9 (Peripheral Pin Select Output 9) ................. 170 SEVTCMP (PWM Special Event Compare) ............. 194 SPIxCON1 (SPIx Control 1) ..................................... 211 SPIxCON2 (SPIx Control 2) ..................................... 213 SPIxSTAT (SPIx Status and Control) ....................... 210 SR (CPU STATUS) .................................................... 92 SR (CPU Status) ........................................................ 24 STRIGx (PWMx Secondary Trigger Compare Value) ............................................... 206 T1CON (Timer1 Control) .......................................... 176 TRGCONx (PWMx Trigger Control) ......................... 201 TRIGx (PWMx Primary Trigger Compare Value) ..... 206 TxCON (Timer Control, x = 2)................................... 180 TyCON (Timer Control, y = 3)................................... 181 UxMODE (UARTx Mode) ......................................... 224 UxSTA (UARTx Status and Control) ........................ 226 Reset Configuration Mismatch.............................................. 86 Illegal Opcode....................................................... 79, 86 Trap Conflict ............................................................... 85 Uninitialized W Register ....................................... 79, 86 Reset Sequence ................................................................. 87 Resets ................................................................................ 79 Revision History................................................................ 321 S Serial Peripheral Interface (SPI) ....................................... 209 Software RESET Instruction (SWR) ................................... 85 Software Simulator (MPLAB SIM) .................................... 272 Software Stack Pointer, Frame Pointer CALL Stack Frame ..................................................... 63 Special Features of the CPU ............................................ 255 Symbols Used in Opcode Descriptions ............................ 264 T Temperature and Voltage Specifications AC............................................................................. 284 Timer1 .............................................................................. 175 Timer2/3 ........................................................................... 177 Timing Diagrams A/D Conversion per Input ......................................... 305 Brown-out Situations .................................................. 85 External Clock .......................................................... 285 High-Speed PWM..................................................... 294 High-Speed PWM Fault ............................................ 294 I/O............................................................................. 287 I2Cx Bus Data (Master Mode) .................................. 300 I2Cx Bus Data (Slave Mode) .................................... 302 I2Cx Bus Start/Stop Bits (Master Mode)................... 300 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 302 Input Capture (CAPx) ............................................... 292 OC/PWM .................................................................. 293 Output Compare (OCx) ............................................ 292 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 288 SPIx Master Mode (CKE = 0) ................................... 295 SPIx Master Mode (CKE = 1) ................................... 296 SPIx Slave Mode (CKE = 0) ..................................... 297 SPIx Slave Mode (CKE = 1) ..................................... 298 (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 339 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Timer1, 2, 3 External Clock....................................... 290 Timing Requirements External Clock ........................................................... 285 I/O ............................................................................. 287 Input Capture ............................................................ 292 Timing Specifications 10-Bit A/D Conversion Requirements ....................... 305 High-Speed PWM Requirements .............................. 294 I2Cx Bus Data Requirements (Master Mode) ........... 301 I2Cx Bus Data Requirements (Slave Mode) ............. 303 Output Compare Requirements ................................ 292 PLL Clock.................................................................. 286 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements.................................................... 289 Simple OC/PWM Mode Requirements ..................... 293 SPIx Master Mode (CKE = 0) Requirements ............ 295 SPIx Master Mode (CKE = 1) Requirements ............ 296 SPIx Slave Mode (CKE = 0) Requirements .............. 297 SPIx Slave Mode (CKE = 1) Requirements.............. 299 Timer1 External Clock Requirements ....................... 290 Timer2 External Clock Requirements ....................... 291 Timer3 External Clock Requirements ....................... 291 U Universal Asynchronous Receiver Transmitter (UART) ... 223 Using the RCON Status Bits............................................... 86 V Voltage Regulator (On-Chip) ............................................ 258 W Watchdog Time-out Reset (WDTO).................................... 85 Watchdog Timer (WDT)............................................ 255, 259 Programming Considerations ................................... 259 WWW Address ................................................................. 331 WWW, On-Line Support ..................................................... 12 DS70318D-page 340 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software. * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing. * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 341 DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS70318D FAX: (______) _________ - _________ Device: DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70318D-page 342 Preliminary (c) 2009 Microchip Technology Inc. DSPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 06 GS1 02 T E / SP - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Examples: a) dsPIC33FJ06GS102-E/SP: SMPS dsPIC33, 6-Kbyte program memory, 28-pin, Extended temp.,SPDIP package. Architecture: 33 = = = = = = = = = = = 16-bit Digital Signal Controller Flash program memory, 3.3V Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family 18-pin 28-pin 44-pin -40C to+85C (Industrial) -40C to+125C (Extended) Flash Memory Family: FJ Product Group: GS1 GS2 GS4 GS5 01 02 04 I E Pin Count: Temperature Range: Package: SO SP ML MM PT = = = = = Plastic Small Outline - Wide - 7.50 mm body (SOIC) Skinny Plastic Dual In-Line - 300 mil body (SPDIP) Plastic Quad Flat, No Lead Package - 8x8 mm body (QFN) Plastic Quad Flat, No Lead Package - 6x6x0.9 mm body (QFN-S) Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP) (c) 2009 Microchip Technology Inc. Preliminary DS70318D-page 343 Worldwide Sales and Service AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 02/04/09 DS70318D-page 344 Preliminary (c) 2009 Microchip Technology Inc. |
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